DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species IA (Fig. 13, Claims 1-16 and 21-24) in the reply filed on 01/23/2026 is acknowledged.
Claim Objections
Claim 5 and 12 are objected to because of the following informalities:
Claims 5 and 12 recites “dielectric layer comprise” which is grammatically incorrect. The verb comprise is plural which is inconsistent with dielectric layer which is singular. The verb should be amended to singular “comprises”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 16 recites the limitation "the CESL" in line 1. There is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination, the Examiner will treat Claim 16 to be dependent on Claim 15.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2022/0273114 A1) in view of Jagannathan (US 9,761,722 B1).
Regarding Claim 1 Chen (Fig. 16) discloses a semiconductor structure, comprising:
a substrate (202) [0014];
a first semiconductor layer ( over the substrate;
a second semiconductor layer over the first semiconductor layer and comprising a channel region (region around and under 240 “The suspended semiconductor layers 210A are also referred to as channel semiconductor layers 210A.”) [0031-0032] sandwiched between a first source/drain region (a source/drain region around left 230 “ epitaxial S/D layers 230 include a semiconductor material” [0026]) and a second source/drain region (a source/drain region around right 230 “ epitaxial S/D layers 230 include a semiconductor material” [0026]);
a first plurality of nanostructures (210, 240) disposed over the channel region (region under 240);
a first leakage block layer (left 226) disposed over the first source/drain region (region under source/drain regions 230);
a second leakage block layer (right 226) disposed over the second source/drain region (region under 240);
a dielectric layer (ILD layer 232) disposed on the first leakage block layer (left 226);
a first source/drain feature (left 230) disposed on the dielectric layer (232) and in contact with first sidewalls of the first plurality of nanostructures (210, 240); and
a second source/drain feature (right 230) disposed on the second leakage block layer (right 226) and in contact with second sidewalls of the first plurality of nanostructures (210, 240), wherein
the first leakage block layer and the second leakage block layer (left and right 230) comprise an undoped semiconductor material. [0025]
Chen does not explicitly disclose a first semiconductor layer over the substrate; a second semiconductor layer over the first semiconductor layer and comprising a channel region
Jagannathan (Fig. 4) discloses a first semiconductor layer (203) over a substrate (202); a second semiconductor layer (204, 207, 208) over the first semiconductor layer (203).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor structure in Chen in view of Jagannathan such that there is a first semiconductor layer over the substrate; a second semiconductor layer over the first semiconductor layer and comprising a channel region in order to enhance stress in the source and drain regions and improve performance of three-dimensional FET devices (Colum 2, lines 65-67, Column 3, lines 1-5)
Regarding Claim 3, Chen in view of Jagannathan discloses the semiconductor structure of claim 1, wherein
the substrate and the second semiconductor layer comprise silicon (Si), wherein the first semiconductor layer comprises silicon germanium (SiGe). (“The substrate 101 may be a silicon (Si) substrate. An epitaxially gown Si layer 103 is shown above the SiGe layer 102” Jagannathan)
Claim(s) 2, 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2022/0273114 A1) in view of Jagannathan (US 9,761,722 B1) and further in view of Chiang et al. (US 2021/0305252 A1).
Regarding Claim 2, Chen in view of Jagannathan discloses the semiconductor structure of claim 1, wherein
the first source/drain feature and the second source/drain feature comprise silicon germanium (SiGe) and a p-type dopant. [0026]
Chen in view of Jagannathan does not explicitly disclose a p-type dopant
Chiang (Fig. 10B) discloses source/drain feature (260) comprise silicon germanium (SiGe) and a p-type dopant [0049]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor structure in Chen in view of Jagannathan and such that there is a first semiconductor layer over the substrate; a second semiconductor layer over the first semiconductor layer and comprising a channel region in order to manufacture p-type transistors [0049].
Regarding Claim 4, Chen in view of Jagannathan discloses the semiconductor structure of claim 1, wherein
Chen in view of Jagannathan does not explicitly disclose the first leakage block layer and the second leakage block layer comprise undoped germanium (Ge) or undoped silicon germanium (SiGe).
Chiang (Fig. 34B) discloses a leakage block layer comprise undoped germanium (Ge) or undoped silicon germanium (SiGe). (“the semiconductor layer 502 includes undoped silicon germanium for both nFETs and pFETs“) [0091]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor structure in Chen in view of Jagannathan and Chiang such that the first leakage block layer and the second leakage block layer comprise undoped germanium (Ge) or undoped silicon germanium (SiGe). in order to enhance etch selectivity during the etching process to etch silicon and so it can be applied to both nFET regions and pFET regions. [0091]
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2022/0273114 A1) in view of Jagannathan (US 9,761,722 B1) and further in view of Bourjot et al. (US 2019/0341448 A1)
Regarding Claim 5, Chen in view of Jagannathan discloses the semiconductor structure of claim 1, wherein
Chen in view of Jagannathan does not explicitly disclose the dielectric layer comprise silicon nitride.
Bourjot (Fig. 4) discloses a dielectric layer (150) comprise silicon nitride.[0021].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor structure in Chen in view of Jagannathan and Chiang such that the dielectric layer comprise silicon nitride in order to form inner spacers on edges of SiGe layers [0021] and since the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (See MPEP 2144.07).
Claim(s) 6-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2022/0273114 A1) in view of Jagannathan (US 9,761,722 B1) and further in view of Lin et al. (US 2022/0216340 A1).
Regarding Claim 6, Chen in view of Jagannathan discloses the semiconductor structure of claim 1, further comprising:
a first gate structure (244) wrapping around at least one of the first plurality of nanostructures;
a middle dielectric layer over the first plurality of nanostructures;
a second plurality of nanostructures over the middle dielectric layer; and
a second gate structure wrapping around at least one of the second plurality of nanostructures, wherein
a composition of the first gate structure is different from a composition of the second gate structure.
Chen in view of Jagannathan does not explicitly disclose a middle dielectric layer over the first plurality of nanostructures; a second plurality of nanostructures over the middle dielectric layer; and a second gate structure wrapping around at least one of the second plurality of nanostructures, wherein a composition of the first gate structure is different from a composition of the second gate structure.
Chen in view of Jagannathan does a first gate structure (264 around 266P) wrapping around at least one of the first plurality of nanostructures (266P);
a middle dielectric layer (264 between 266P and 266N) over the first plurality of nanostructures (266P);
a second plurality of nanostructures (266N) over the middle dielectric layer (264 between 266P and 266N); and
a second gate structure (264 around 266N) wrapping around at least one of the second plurality of nanostructures (266N), wherein
a composition of the first gate structure (266P) is different from a composition of the second gate structure (266N). [0034]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor structure in Chen in view of Jagannathan and Lin such that a first gate structure (244) wrapping around at least one of the first plurality of nanostructures; a middle dielectric layer over the first plurality of nanostructures; a second plurality of nanostructures over the middle dielectric layer; and a second gate structure wrapping around at least one of the second plurality of nanostructures, wherein a composition of the first gate structure is different from a composition of the second gate structure in order to have complementary field effect transistors (C-FET) where an n-type multi-gate transistor and a p-type multi-gate transistor are stacked vertically, one over the other. [0003]
Regarding Claim 7, Chen in view of Jagannathan and Lin discloses the semiconductor structure of claim 6, wherein
the first gate structure comprises titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), aluminum (Al), tungsten nitride (WN), zirconium silicide (ZrSi.sub.2), molybdenum silicide (MoSi.sub.2), tantalum silicide (TaSi.sub.2), or nickel silicide (NiSi.sub.2), wherein
the second gate structure comprises titanium (Ti), aluminum (Al), silver (Ag), manganese (Mn), zirconium (Zr), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicide nitride (TaSiN), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), or titanium aluminum nitride (TiAlN).[0034 Lin]
Regarding Claim 8, Chen in view of Jagannathan and Lin discloses the semiconductor structure of claim 6.
Chen in view of Jagannathan and Lin as previously combined does not explicitly disclose a third source/drain feature disposed over the first source/drain feature; and a fourth source/drain feature disposed over the second source/drain feature, wherein the second plurality of nanostructures are sandwiched between and in contact with the third source/drain feature and the fourth source/drain feature.
Lin (Fig. 18) discloses a third source/drain feature (248-1 Lin) disposed over the first source/drain feature (228-1); and
a fourth source/drain feature (248-2 Lin) disposed over the second source/drain feature (228-2 Lin), wherein
the second plurality of nanostructures (226N) are sandwiched between and in contact with the third source/drain feature (248-1 Lin) and the fourth source/drain feature (248-2 Lin).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor structure in Chen in view of Jagannathan and Lin such that a third source/drain feature disposed over the first source/drain feature; and a fourth source/drain feature disposed over the second source/drain feature, wherein the second plurality of nanostructures are sandwiched between and in contact with the third source/drain feature and the fourth source/drain feature in order to have complementary field effect transistors (C-FET) where an n-type multi-gate transistor and a p-type multi-gate transistor are stacked vertically, one over the other. [0003]
Regarding Claim 9, Chen in view of Jagannathan and Lin discloses the semiconductor structure of claim 8, wherein the third source/drain feature and the fourth source/drain feature comprise silicon (Si) and an n-type dopant. (“the first top source/drain feature 248-1 is an n-type source/drain feature and may include silicon (Si) doped with an n-type dopant” ) [0027]
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2022/0273114 A1) in view of Chen et al. (US 2022/0165730 A1; hereinafter Chen/730).
Regarding Claim 21, Chen (Fig. 15) discloses a semiconductor structure, comprising:
a substrate (202);
a first base portion and a second base portion (left and right fins in Fig. 15) extending from the substrate (202);
an isolation feature (204) disposed over the substrate (202) and interfacing sidewalls of the first base portion and the second base portion (left and right fins);
a first leakage block layer (left 226) over the first base portion;
a second leakage block layer (right 226) over the second base portion;
a sealing layer (232) extending over and interfacing the first leakage block layer (226);
a first source/drain feature (230) over the sealing layer (226);
a second source/drain (230) feature over and interfacing the second leakage block layer (right 226); and
Chen does not explicitly disclose a contact etch stop layer (CESL) extending continuously over the sealing layer, the first source/drain feature, the isolation feature, and the second source/drain feature.
Chen/730 (Fig. 22) discloses a contact etch stop layer (CESL) (2202) extending continuously over a sealing layer (space between 1602 and 702), a source/drain feature (1602), an isolation feature (402).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor structure in Chen in view of Chen/730 such that a contact etch stop layer (CESL) extending continuously over the sealing layer, the first source/drain feature, the isolation feature, and the second source/drain feature in order to to selectively remove the sacrificial gate electrode layer [0062].
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2022/0273114 A1) in view of Chen et al. (US 2022/0165730 A1; hereinafter Chen/730) and further in view of Bourjot et al. (US 2019/0341448 A1)
Regarding Claim 5, Chen in view of Chen 730 discloses the semiconductor structure of claim 21, wherein
Chen in view of Chen730 does not explicitly disclose the sealing layer comprises silicon nitride.
Bourjot (Fig. 4) discloses a sealing layer (150) comprises silicon nitride.[0021].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor structure in Chen in view of Chen/730 and Chiang such that the sealing layer comprises silicon nitride in order to form inner spacers on edges of SiGe layers [0021] and since the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (See MPEP 2144.07).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2022/0273114 A1) in view of Chen et al. (US 2022/0165730 A1; hereinafter Chen/730) and further in view of Chiang et al. (US 2021/0305252 A1).
Regarding Claim 24, Chen in view of Chen/730 discloses semiconductor structure of claim 21, wherein
Chen in view of Chen/730 does not explicitly disclose the first leakage block layer and the second leakage block layer comprise undoped silicon, undoped silicon germanium, or undoped germanium.
Chiang (Fig. 34B) discloses a leakage block layer comprise undoped germanium (Ge) or undoped silicon germanium (SiGe). (“the semiconductor layer 502 includes undoped silicon germanium for both nFETs and pFETs“) [0091]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor structure in Chen in view of Chen730/ and Chiang such that the first leakage block layer and the second leakage block layer comprise undoped silicon, undoped silicon germanium, or undoped germanium in order to enhance etch selectivity during the etching process to etch silicon and so it can be applied to both nFET regions and pFET regions. [0091]
Allowable Subject Matter
Claim 10-15 are allowed.
With regards to claim 10, none of the prior art teaches or suggests, alone or in combination, “first spacer features disposed along sidewalls of the first leakage block layer; second spacer features disposed along sidewalls of the second leakage block layer;”….“a first source/drain feature disposed over the dielectric layer; and a second source/drain feature disposed over the second leakage block layer and the second spacer features, wherein the first source/drain feature is spaced apart from the first leakage block layer and the first spacer features by the dielectric layer, wherein the second source/drain feature is in direct contact with the second leakage block layer and the second spacer features.” in the combination required by the claim.
Claims 11-15 are allowed by virtue of their dependency on the independent claim 10.
Claim 22 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Miao et al. (US 2020/0052124 A1) and Yang et al. (US 2022/0310806 A1) discloses FED with local isolation/leakage current clocking layers under source/drain regions.
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/DMITRIY YEMELYANOV/Examiner, Art Unit 2891