DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Moon et al. (US 2021/0234119) (hereafter Moon).
Regarding claim 1, Moon discloses a display device comprising:
a pixel circuit layer (layers vertically from 105 to VIA2 in Fig. 4) comprising a first transistor (TFT and 162 in Fig. 4, paragraphs 0097 and 0098) and a first auxiliary layer (vertical portion of PXE in Fig. 4, paragraph 0103); and
a display element layer (EMD in Fig. 4, paragraph 0101) on the pixel circuit layer (layers vertically from 105 to VIA2 in Fig. 4), and comprising at least one light emitting element (EML in Fig. 4, paragraph 0101), wherein the display element layer (EMD in Fig. 4) comprises:
a first pixel electrode (horizontal portion of PXE in Fig. 4, paragraph 0103) electrically connected to a first end (bottom surface of EML in Fig. 4) of the light emitting element (EML in Fig. 4); and
a second pixel electrode (CME in Fig. 4, paragraph 0101) electrically connected to a second end (top surface of EML in Fig. 4) of the light emitting element (EML in Fig. 4),
wherein the first transistor (TFT and 162 in Fig. 4) comprises:
a semiconductor pattern 110 (Fig. 4, paragraph 0087);
a first gate insulating layer 121 (Fig. 4, paragraph 0087) on the semiconductor pattern 110 (Fig. 4);
a gate electrode (bottom layer of 130 in Fig. 4, paragraph 0092, wherein “multiple layers”) on the first gate insulating layer 121 (Fig. 4); and
a first transistor electrode (152 and 162 in Fig. 4, paragraph 0096) and a second transistor electrode (bottom layer of 151 in Fig. 4, paragraph 0096, wherein “multiple layers”) connected to the semiconductor pattern 110 (Fig. 4),
wherein the first transistor electrode (152 and 162 in Fig. 4) is connected to the second pixel electrode (CME in Fig. 4) by the first auxiliary layer (vertical portion of PXE in Fig. 4), and
wherein the first auxiliary layer (vertical portion of PXE in Fig. 4) is between the first transistor electrode (152 and 162 in Fig. 4) and the second pixel electrode (CME in Fig. 4).
Regarding claim 2, Moon further discloses the display device according to claim 1, wherein the first auxiliary layer (vertical portion of PXE in Fig. 4, paragraph 0103, wherein “stacked structure (ITO/Ag/ITO)”) comprises indium tin oxide (ITO).
Regarding claim 3, Moon further discloses the display device according to claim 2, wherein the first auxiliary layer (vertical portion of PXE in Fig. 4) is directly on the first transistor electrode (152 and 162 in Fig. 4).
Regarding claim 4, Moon further discloses the display device according to claim 3, wherein the first transistor electrode (152 and 162 in Fig. 4) and the second transistor electrode (bottom layer of 151 in Fig. 4, paragraph 0096, wherein “multiple layers”) comprise (see paragraph 0096, wherein “any one of aluminum (Al), gold (Au), and copper (Cu) or an alloy thereof”) titanium (Ti) and copper (Cu).
Regarding claim 5, Moon further discloses the display device according to claim 3, wherein the pixel circuit layer (layers vertically from 105 to VIA2 in Fig. 4) further comprises:
a first bottom metal layer (middle layer of 151 in Fig. 4, paragraph 0096, wherein “multiple layers”) on a substrate 101 (Fig. 4, paragraph 0083), and electrically connected to the second transistor electrode (bottom layer of 151 in Fig. 4, paragraph 0096, wherein “multiple layers”);
a buffer layer (top layer of 151 in Fig. 4, paragraph 0096, wherein “multiple layers”) covering the first bottom metal layer (middle layer of 151 in Fig. 4, paragraph 0096, wherein “multiple layers”); and
a conductive pattern 45 (Fig. 4, paragraph 0065) at a same layer as the gate electrode (bottom layer of 130 in Fig. 4, paragraph 0092, wherein “multiple layers”), and electrically connected (see paragraph 0080, wherein “The common electrode CME may be provided with a second power voltage having a low potential through the second power supply line 45 electrically connected to the auxiliary electrode APE.”) to the first bottom metal layer (bottom layer of 151 in Fig. 4, paragraph 0096, wherein “multiple layers”),
wherein the display element layer (EMD in Fig. 4) further comprises:
a first alignment electrode (bottom ITO of APE in Fig. 4, paragraph 0113, wherein “ITO/Ag/ITO”) under the first pixel electrode (top ITO of PXE in Fig. 4, paragraph 0103, wherein “stacked structure (ITO/Ag/ITO)”); and
a second alignment electrode (top ITO of APE in Fig. 4, paragraph 0113, wherein “ITO/Ag/ITO”) under the second pixel electrode (CME in Fig. 4), and wherein one alignment electrode (bottom ITO of APE in Fig. 4) from among the first alignment electrode (bottom ITO of APE in Fig. 4) and the second alignment electrode (top ITO of APE in Fig. 4) is directly connected to the conductive pattern 45 (Fig. 4).
Regarding claim 6, Moon further discloses the display device according to claim 5, wherein the pixel circuit layer (layers vertically from 105 to VIA2 in Fig. 4) further comprises a second auxiliary layer (bottom portion of vertical portion of PXE in Fig. 4, paragraph 0103), wherein the second auxiliary layer (bottom portion of vertical portion of PXE in Fig. 4) is directly on the second transistor electrode (152 and 162 in Fig. 4), and wherein the first auxiliary layer (top portion of vertical portion of PXE in Fig. 4, paragraph 0103, wherein “stacked structure (ITO/Ag/ITO)”) and the second auxiliary layer (bottom portion of vertical portion of PXE in Fig. 4, paragraph 0103, wherein “stacked structure (ITO/Ag/ITO)”) are at a same layer (layers vertically from 105 to VIA2 in Fig. 4) and comprise a same material.
Regarding claim 7, Moon further discloses the display device according to claim 5, wherein the first auxiliary layer (top portion of vertical portion of PXE in Fig. 4, paragraph 0103, wherein “stacked structure (ITO/Ag/ITO)”) is not on the conductive pattern 45 (Fig. 4).
Regarding claim 8, Moon further discloses the display device according to claim 7, wherein the first transistor electrode (152 and 162 in Fig. 4) and the second transistor electrode (bottom layer of 151 in Fig. 4, paragraph 0096, wherein “multiple layers”) are in a layer different from a layer in which the gate electrode (bottom layer of 130 in Fig. 4, paragraph 0092, wherein “multiple layers”) is located.
Regarding claim 9, Moon further discloses the display device according to claim 5, wherein the pixel circuit layer (layers vertically from 105 to VIA2 in Fig. 4) further comprises a first insulating layer 121 (Fig. 4, paragraph 0087) on (see Fig. 4, wherein 121 is laterally on 151) the buffer layer (top layer of 151 in Fig. 4, paragraph 0096, wherein “multiple layers”), wherein the conductive pattern 45 (Fig. 4) is on the first insulating layer 121 (Fig. 4), and wherein the gate electrode (bottom layer of 130 in Fig. 4, paragraph 0092, wherein “multiple layers”) and the conductive pattern 45 (Fig. 4) are at a same layer (layers vertically from 105 to VIA2 in Fig. 4).
Regarding claim 10, Moon further discloses the display device according to claim 9, wherein the gate electrode (bottom layer of 130 in Fig. 4), the first transistor electrode (152 and 162 in Fig. 4), the second transistor electrode (bottom layer of 151 in Fig. 4, paragraph 0096, wherein “multiple layers”), and the conductive pattern 45 (Fig. 4) are at a same layer (layers vertically from 105 to VIA2 in Fig. 4).
Regarding claim 11, Moon (utilized different elements for a first transistor electrode and a second transistor electrode as applied in claim 1 in the above) discloses a display device comprising:
a pixel circuit layer (layers vertically from 105 to VIA2 in Fig. 4) comprising a first transistor (TFT and 162 in Fig. 4, paragraphs 0097 and 0098) and a first auxiliary layer (vertical portion of PXE in Fig. 4, paragraph 0103); and
a display element layer (EMD in Fig. 4, paragraph 0101) on the pixel circuit layer (layers vertically from 105 to VIA2 in Fig. 4), and comprising at least one light emitting element (EML in Fig. 4, paragraph 0101), wherein the display element layer (EMD in Fig. 4) comprises:
a first pixel electrode (horizontal portion of PXE in Fig. 4, paragraph 0103) electrically connected to a first end (bottom surface of EML in Fig. 4) of the light emitting element (EML in Fig. 4); and
a second pixel electrode (CME in Fig. 4, paragraph 0101) electrically connected to a second end (top surface of EML in Fig. 4) of the light emitting element (EML in Fig. 4),
wherein the first transistor (TFT and 162 in Fig. 4) comprises:
a semiconductor pattern 110 (Fig. 4, paragraph 0087);
a first gate insulating layer 121 (Fig. 4, paragraph 0087) on the semiconductor pattern 110 (Fig. 4);
a gate electrode (bottom layer of 130 in Fig. 4, paragraph 0092, wherein “multiple layers”) on the first gate insulating layer 121 (Fig. 4); and
a first transistor electrode (bottom layer of 151 in Fig. 4, paragraph 0096, wherein “multiple layers”) and a second transistor electrode (top layer of 152 and 162 in Fig. 4, paragraph 0096, wherein “multiple layers”) connected to the semiconductor pattern 110 (Fig. 4),
wherein the first transistor electrode (bottom layer of 151 in Fig. 4) is connected to the second pixel electrode (CME in Fig. 4) by the first auxiliary layer (vertical portion of PXE in Fig. 4), and
wherein the first auxiliary layer (vertical portion of PXE in Fig. 4) is between (see Fig. 4, wherein vertical portion of PXE is diagonally between 151 and CME) the first transistor electrode (bottom layer of 151 in Fig. 4) and the second pixel electrode (CME in Fig. 4)wherein the first auxiliary layer (vertical portion of PXE in Fig. 4, paragraph 0103, wherein “stacked structure (ITO/Ag/ITO)”) comprises indium tin oxide (ITO);
wherein the pixel circuit layer (layers vertically from 105 to VIA2 in Fig. 4) comprises: a first bottom metal layer (bottom layer of 152 in Fig. 4, paragraph 0096, wherein “multiple layers”) under the second transistor electrode (top layer of 152 and 162 in Fig. 4, paragraph 0096, wherein “multiple layers”); and a buffer layer (VIA1 in Fig. 4, paragraph 0097) covering the first bottom metal layer (bottom layer of 152 in Fig. 4), and wherein the first auxiliary layer (vertical portion of PXE in Fig. 4) is directly on the first bottom metal layer (bottom layer of 152 in Fig. 4).
Regarding claim 12, Moon further discloses the display device according to claim 11, wherein the first transistor electrode (bottom layer of 151 in Fig. 4, paragraph 0096, wherein “multiple layers”), the second transistor electrode (top layer of 152 and 162 in Fig. 4, paragraph 0096, wherein “multiple layers”), and the first bottom metal layer (bottom layer of 152 in Fig. 4) comprise (see paragraph 0096, wherein “any one of aluminum (Al), gold (Au), and copper (Cu) or an alloy thereof”) titanium (Ti) and copper (Cu).
Regarding claim 13, Moon further discloses the display device according to claim 12, wherein the display element layer (EMD in Fig. 4) comprises: a first alignment electrode (bottom layer of PXE in Fig. 4, paragraph 0092, wherein “multiple layers”) under the first pixel electrode (horizontal portion of PXE in Fig. 4); and a second alignment electrode (middle layer of PXE in Fig. 4, paragraph 0092, wherein “multiple layers”) under the second pixel electrode (CME in Fig. 4), and wherein one alignment electrode (bottom layer of PXE in Fig. 4) from among the first alignment electrode (bottom layer of PXE in Fig. 4) and the second alignment electrode (middle layer of PXE in Fig. 4) is directly connected to the second transistor electrode (top layer of 152 and 162 in Fig. 4, paragraph 0096, wherein “multiple layers”).
Regarding claim 14, Moon further discloses the display device according to claim 13, wherein the pixel circuit layer (layers vertically from 105 to VIA2 in Fig. 4) further comprises: a second bottom metal layer (middle second top layer of 152 in Fig. 4, paragraph 0096, wherein “multiple layers”) spaced (see paragraph 0096, wherein “multiple layers” such that middle lower layer of 152 is between bottom layer of 152 and middle second upper layer of 152) from the first bottom metal layer (bottom layer of 152 in Fig. 4); and a second auxiliary layer (middle top layer of 152 in Fig. 4, paragraph 0096, wherein “multiple layers”) directly on the second bottom metal layer (middle second top layer of 152 in Fig. 4), and wherein the second transistor electrode (top layer of 152 and 162 in Fig. 4, paragraph 0096, wherein “multiple layers”) is directly connected to the second auxiliary layer (middle top layer of 152 in Fig. 4).
Regarding claim 15, Moon further discloses the display device according to claim 14, wherein the gate electrode (bottom layer of 130 in Fig. 4, paragraph 0092, wherein “multiple layers”), the first transistor electrode (bottom layer of 151 in Fig. 4, paragraph 0096, wherein “multiple layers”), and the second transistor electrode (top layer of 152 and 162 in Fig. 4, paragraph 0096, wherein “multiple layers”) are at a same layer (layers vertically from 105 to VIA2 in Fig. 4).
Regarding claim 16, Moon further discloses the display device according to claim 2, wherein the pixel circuit layer (layers vertically from 105 to VIA2 in Fig. 4) comprises:
a first bottom metal layer (middle layer of 151 in Fig. 4, paragraph 0096, wherein “multiple layers”) on a substrate 101 (Fig. 4, paragraph 0083); and
a buffer layer (VIA1 in Fig. 4, paragraph 0112) covering the first bottom metal layer (middle layer of 151 in Fig. 4), and wherein the first transistor (TFT and 162 in Fig. 4) is on the buffer layer (top layer of 151 in Fig. 4),
wherein the display element layer (EMD in Fig. 4) comprises: a first alignment electrode (Ag of PXE in Fig. 4, paragraph 0103, wherein “stacked structure (ITO/Ag/ITO)”) under the first pixel electrode (top ITO of PXE in Fig. 4, paragraph 0103, wherein “stacked structure (ITO/Ag/ITO)”); and a second alignment electrode (bottom ITO of layer of PXE in Fig. 4, paragraph 0103, wherein “stacked structure (ITO/Ag/ITO)”) under the second pixel electrode (CME in Fig. 4), and wherein one alignment electrode (bottom ITO of layer of PXE in Fig. 4, paragraph 0103, wherein “stacked structure (ITO/Ag/ITO)”) from among the first alignment electrode (Ag of PXE in Fig. 4, paragraph 0103, wherein “stacked structure (ITO/Ag/ITO)”) and the second alignment electrode (bottom ITO of layer of PXE in Fig. 4, paragraph 0103, wherein “stacked structure (ITO/Ag/ITO)”) is directly connected to the first bottom metal layer (top layer of 162 in Fig. 4) through a contact hole (region where vertical portion of PXE is formed in Fig. 4).
Regarding claim 17, Moon discloses a display device comprising:
a substrate 101 (Fig. 4, paragraph 0083);
a first bottom metal layer 45 (Fig. 4, paragraph 0111) on the substrate 101 (Fig. 4);
a first auxiliary layer (bottom ITO of APE in Fig. 4, paragraph 0113, wherein “ITO/Ag/ITO”) directly on the first bottom metal layer 45 (Fig. 4);
a buffer layer (VIA1 in Fig. 4, paragraph 0097) covering the first bottom metal layer 45 (Fig. 4);
a first transistor (TFT and 162 in Fig. 4, paragraphs 0097 and 0098) on the buffer layer (VIA1 in Fig. 4);
a light emitting element (EML in Fig. 4, paragraph 0101) on the first transistor (TFT and 162 in Fig. 4);
a first pixel electrode (top ITO of PXE in Fig. 4, paragraph 0103, wherein “stacked structure (ITO/Ag/ITO)”) electrically connected to a first end (bottom of EML in Fig. 4) of the light emitting element (EML in Fig. 4); and
a second pixel electrode (CME in Fig. 4, paragraph 0101) electrically connected to a second end (top of EML in Fig. 4) of the light emitting element (EML in Fig. 4), wherein the first transistor (TFT and 162 in Fig. 4) comprises a first transistor electrode 151 (Fig. 4, paragraph 0096) and a second transistor electrode (152 and 162 in Fig. 4, paragraph 0098), and wherein the second pixel electrode (CME in Fig. 4) is connected (see paragraph 0080, wherein “The common electrode CME may be provided with a second power voltage having a low potential through the second power supply line 45 electrically connected to the auxiliary electrode APE”) to the first bottom metal layer 45 (Fig. 4) by the first auxiliary layer (APE in Fig. 4).
Regarding claim 18, Moon further discloses the display device according to claim 17, wherein the first auxiliary layer (bottom ITO of APE in Fig. 4, paragraph 0113, wherein “ITO/Ag/ITO”) comprises indium tin oxide (ITO).
Regarding claim 19, Moon further discloses the display device according to claim 18, further comprising a second bottom metal layer (bottom layer of 135 in Fig. 4, paragraph 0091, wherein “the first signal line 135 may be formed as a single layer or multiple layers”) and a fourth bottom metal layer (top layer of 135 in Fig. 4, paragraph 0091) on the substrate 101 (Fig. 4); a first alignment electrode (AG of PXE in Fig. 4, paragraph 0103, wherein “stacked structure (ITO/Ag/ITO)”) under the first pixel electrode (PXE in Fig. 4); and a second alignment electrode (bottom ITO of PXE in Fig. 4, paragraph 0103, wherein “stacked structure (ITO/Ag/ITO)”) under the second pixel electrode (CME in Fig. 4), wherein one alignment electrode (bottom ITO of PXE in Fig. 4) from among the first alignment electrode (AG of PXE in Fig. 4) and the second alignment electrode (bottom ITO of PXE in Fig. 4) is directly connected to one transistor electrode (152 and 162 in Fig. 4) of the first transistor electrode 151 (Fig. 4) and the second transistor electrode (152 and 162 in Fig. 4), wherein the first transistor electrode 151 (Fig. 4) is connected to the fourth bottom metal layer by a fourth auxiliary layer on the fourth bottom metal layer (top layer of 135 in Fig. 4), and wherein the second transistor electrode (152 and 162 in Fig. 4) is electrically connected to the second bottom metal layer (bottom layer of 135 in Fig. 4) by a second auxiliary layer (top ITO of APE in Fig. 4, paragraph 0113, wherein “ITO/Ag/ITO”) on the second bottom metal layer 45 (Fig. 4).
Regarding claim 20, Moon discloses a display device comprising:
a substrate 101 (Fig. 4, paragraph 0083);
a first bottom metal layer 45 (Fig. 4, paragraph 0111) on the substrate 101 (Fig. 4);
a first auxiliary layer (APE in Fig. 4, paragraph 0079) directly on the first bottom metal layer 45 (Fig. 4);
a buffer layer (VIA1 in Fig. 4, paragraph 0097) covering the first bottom metal layer 45 (Fig. 4);
a first transistor (TFT and 162 in Fig. 4, paragraphs 0097 and 0098) on the buffer layer (VIA1 in Fig. 4), and comprising a first transistor electrode 130 (Fig. 4, paragraph 0111) and a second transistor electrode 140 (Fig. 4, paragraph 0111);
a light emitting element (EML in Fig. 4, paragraph 0101) on the first transistor (TFT and 162 in Fig. 4);
a first pixel electrode (PXE in Fig. 4, paragraph 0101) electrically connected to a first end (bottom of EML in Fig. 4) of the light emitting element (EML in Fig. 4); and
a second pixel electrode (CME in Fig. 4, paragraph 0101) electrically connected to a second end (top of EML in Fig. 4) of the light emitting element (EML in Fig. 4), wherein the second pixel electrode (CME in Fig. 4) is connected (see paragraph 0080, wherein “The common electrode CME may be provided with a second power voltage having a low potential through the second power supply line 45 electrically connected to the auxiliary electrode APE”) to the first bottom metal layer 45 (Fig. 4) by the first auxiliary layer (APE in Fig. 4), and wherein the second pixel electrode (CME in Fig. 4) directly contacts the first auxiliary layer (APE in Fig. 4).
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813