DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 03/13/2026, 03/03/2026, 07/14/2025, 12/23/2024, and 11/09/2023 is/are in compliance with the provisions 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Response to Remarks
Applicant’s arguments, see pages 8-10, filed 04/23/2026 with respect to the 35 USC § 112 rejection(s) of claim(s) 4 and 10 have been fully considered and are persuasive. Therefore, the 35 USC § 112 rejection of claims 4 and 10 has been withdrawn.
Examiner acknowledges that claim 8 overcomes the prior art of record as explained on pages 10-11 of the Applicants remarks dated 04/23/2026 regarding limitations reciting in part “forming a trench isolation layer.” the 35 USC § 103 rejection of independent claim 8 has been withdrawn.
Examiner acknowledges the amended independent claim 16 as explained on page10 of the Applicants remarks dated 04/23/2026. Claim 16 reciting in part, “forming a trench isolation layer.” Therefore, the 35 USC § 102 rejection of independent claim 16 has been withdrawn.
Examiner acknowledges the new claim 21 has been added, and is based on the structure
of claim 1.
Applicant’s arguments, see pages 12-13, filed 04/23/2026 with respect to the 35 USC § 102 rejection(s) of claim(s) 1-5 and 7 under Ikeda et al. (US 5471083) have been fully considered and are persuasive. However, upon further consideration, a new ground(s) of rejection is made in view of Ikeda et al. (US 5471083) regarding the 35 USC § 102 rejection of independent claim 1 and dependent claim 2.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, and 21 is/are rejected under 35 U.S.C. 102 as being anticipated by Ikeda et al. (US 5471083) herein referred to as Ikeda.
As to claim 1, Ikeda teaches a structure comprising:
a first emitter/collector (E/C) layer (1st emitter region 20, Ikeda, Fig. 1) over a substrate (substrate 1, Ikeda, Fig. 1 ,col 8, lines 8-9, “p type semiconductor substrate 1”)
a base structure (base region (17) + T shaped base interconnection layer (23), Ikeda, Fig. 1, col 7, lines 20-23, ”A base interconnection layer 23 is formed to electrically contact to base extraction electrode layer 17 via another contact hole.”) over the substrate (substrate 1, Ikeda, Fig. 1) and
adjacent to a first horizontal end of the first E/C layer (1st emitter region 20, Ikeda, Fig. 1);
a bounding structure (bounding structure 17, Ikeda, Fig. 1) over the substrate (substrate 1, Ikeda, Fig. 1 ) and adjacent a second horizontal end of the first E/C layer (emitter region 20, Ikeda, Fig. 1), wherein the bounding structure (bounding structure 17, Ikeda, Fig. 1) includes a base material (base material of component 17); and
a spacer (spacer 19, Ikeda , Fig. 1) between the first E/C layer (1st emitter region 20, Ikeda, Fig. 1) and the bounding structure (bounding structure 17, Ikeda, Fig. 1).
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As to claim 2, Ikeda further teaches the structure of claim 1, wherein
the bounding structure (17, Ikeda, Fig. 1) is horizontally between the first E/C layer (20, Ikeda, Fig. 1) and a trench isolation (TI) layer (TI layer 7, Ikeda Fig. 1).
As to claim 3, Ikeda further teaches the structure of claim 2, wherein
the TI layer (7, Ikeda Fig. 1) is horizontally between the bounding structure (17, Ikeda, Fig. 1) and a metal oxide semiconductor field effect transistor (MOSFET) structure (col 6, lines 23-26, Ikeda, Fig. 1 “Referring to FIG. 1, in a semiconductor device according to a first embodiment, an NPN bipolar transistor, a P channel MOS transistor and an N channel MOS transistor are formed adjacent to each other.”).
As to claim 4, Ikeda further teaches the structure of claim 1, wherein
the base structure (base region 17 + 23, Ikeda, Fig. 1 ) includes a substantially T-shaped base material having a base contact thereon (surface between 17 and 23, Ikeda Fig. 1).
As to claim 5, Ikeda further teaches the structure of claim 1, wherein
the bounding structure (17, Ikeda, Fig. 1) is free of conductive contacts thereon (an insulating film is not conductive, (col 6, lines 58-60) “A base extraction electrode layer 17 made of a polycrystalline silicon film” )
As to claim 21, the structure of claim 1, wherein
the first E/C layer (20, Ikeda) is within a first bipolar transistor (Fig. 1, Ikeda) and has a first conductivity type.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. All obviousness rationales stated below are rationales that would have been obvious prior to the earliest effective filing date of the application.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda et al. (US 5471083) herein referred to as Ikeda.
As to claim 7, the structure of claim 1, further comprising:
a second emitter/collector (E/C) (duplicate parts obvious) layer on the substrate (substrate 1, Ikeda, Fig. 1), and having
a first horizontal end adjacent the base structure (base structure 17 + 23, Ikeda Fig. 1) such that
the base structure (base structure 17 + 23, Ikeda Fig. 1) is horizontally between the first E/C layer (Annotated 1st emitter region 20, Ikeda, Fig. 1) and the second E/C layer (Annotated 2nd emitter region 20, Ikeda, Fig. 1); and
an additional bounding structure (additional bounding structure gate electrode 11) over the substrate (substrate 1, Ikeda, Fig. 1) and adjacent a second horizontal end of the second E/C layer (duplicate part obvious ) wherein
the additional bounding structure (additional bounding structure gate electrode 11) includes a gate conductor having a same doping type as, and a different composition from, the base material. (col 11 lines 6-8 “gate electrode 11 made of polycrystalline silicon films 11a and 11b both including n type impurity”)
(Regarding claim(s) 7, Ikeda does not appear to expressly disclose " a second emitter/collector (E/C)"
However, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, that the Ikeda semiconductor device includes a plurality of field effect transistors and a bipolar transistors so as to be used in electronic circuits and projects. It has been held that “mere duplication of parts has no patentable significance unless a new and unexpected result is produced” (See MPEP 2144.04(VI)(B)).)
Allowable Subject Matter
Claim(s) 6 is/are objected to as being dependent upon a rejected base claim 1, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 6, Ikeda further teaches the structure of claim 1, wherein
the bounding structure (17, Ikeda, Fig.1) is on a semiconductor material (layer 2, n-type Fig. 2”)
Ikeda does not teach:
the bounding structure (17, Ikeda, Fig.1) is on a semiconductor material (layer 2, n-type Fig. 2”) having a same conductivity type as the first E/C layer
(Instead, Ikeda teaches the first E/C layer of p-type (substrate 1, Ikeda, Fig. 1, col 8, lines 8-9, “p type semiconductor substrate 1”).
Claims 8 and 16 are allowed. The following is an examiner’s statement of reasons for allowance: The primary reference Ikeda et al. (US 5471083) does not teach all of the limitations of the base claim
As to claim 8, Ikeda further teaches a structure comprising:
a first emitter/collector (E/C) layer (1st emitter N++ region under emitter 20, Ikeda, Fig. 1) over a substrate (substrate 1, Ikeda, Fig. 1)
a base structure (base region 17 + T shaped base interconnection layer 23, Ikeda, Fig. 1) over the substrate (substrate 1, Ikeda, Fig. 1)
a spacer (19) between the first E/C layer (1st emitter region N++ region under layer 20, Ikeda, Fig. 1) and the bounding structure (bounding structure 17).
Ikeda does not teach:
a base structure over the substrate and adjacent a first horizontal end of the first E/C layer, wherein the base structure includes a base material
a bounding structure over the substrate and adjacent the first horizontal end of the first E/C layer, wherein
the bounding structure includes a gate conductor )
having a different composition from the base material; and
As to claim 16, Ikeda does not teach “forming a trench isolation layer in the semiconductor layer, wherein the bounding structure and the first E/C layer are formed on the semiconductor layer so that the bounding structure is horizontally between the first E/C layer and the TI layer.”
The remaining claims (9-15) and (18-20), are allowable at least because they depend from allowable independent claims 8 and 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN SHAW MUSLIM whose telephone number is (571)270-0071. The examiner can normally be reached Mon-Fri 7 am - 4 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on (571) 272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897
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