DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 07/14/2025, 12/23/2024, and 11/09/2023 is/are in compliance with the provisions 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The base structure is described as “a substantially T-shaped base material” having a base content. “Substantially T shaped” is not a distinct description. A more explicit description is suggested unless the Applicant does not intend to disclose a “T-shaped” base material. The Examiner has mapped the base structure of claim 4 with a “substantially T shaped” component (24).
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The Applicant has disclosed additional “E/C” layer. The component should clearly be differentiated as the 1st or 2nd emitter or 1st or 2nd collector, instead of a simply a choice between any emitter or any collector for the additional layer. A more explicit description between one emitter and/or collector is suggested unless the Applicant intends to disclose a choice between any emitter or any collector for the additional layer. The Examiner has assumed the latter by mapping an additional E/C layer with collector (24).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 8-11, and 13-20 is/are rejected under 35 U.S.C. 102 as being anticipated by Ikeda et al. (US 5471083) herein referred to as Ikeda.
As to claim 1, Ikeda teaches a structure comprising:
a first emitter/collector (E/C) layer (1st emitter region 20, Ikeda, Fig. 1) over a substrate (substrate 1, Ikeda, Fig. 1 ,col 8, lines 8-9, “p type semiconductor substrate 1”)
a base structure (base region (17) + T shaped base interconnection layer (23), Ikeda, Fig. 1, col 7, lines 20-23, ”A base interconnection layer 23 is formed to electrically contact to base extraction electrode layer 17 via another contact hole.”) over the substrate (substrate 1, Ikeda, Fig. 1) and
adjacent to a first horizontal end of the first E/C layer (1st emitter region 20, Ikeda, Fig. 1);
a bounding structure (bounding structure 6b, Ikeda, Fig. 1) over the substrate (substrate 1, Ikeda, Fig. 1 ) and adjacent a second horizontal end of the first E/C layer (emitter region 20, Ikeda, Fig. 1), wherein the bounding structure (bounding structure 6b, Ikeda, Fig. 1) includes a base material (base material of component 6b); and
a spacer (spacer 6a, Ikeda , Fig. 1) between the first E/C layer (1st emitter region 20, Ikeda, Fig. 1) and the bounding structure (bounding structure 6b, Ikeda, Fig. 1).
As to claim 2, Ikeda further teaches the structure of claim 1, wherein
the bounding structure (6b, Ikeda, Fig. 1) is horizontally between the first E/C layer (20, Ikeda, Fig. 1) and a trench isolation (TI) layer (TI layer 7, Ikeda Fig. 1).
As to claim 3, Ikeda further teaches the structure of claim 2, wherein
the TI layer (7, Ikeda Fig. 1) is horizontally between the bounding structure (6b, Ikeda, Fig. 1) and a metal oxide semiconductor field effect transistor (MOSFET) structure (col 6, lines 23-26, Ikeda, Fig. 1 “Referring to FIG. 1, in a semiconductor device according to a first embodiment, an NPN bipolar transistor, a P channel MOS transistor and an N channel MOS transistor are formed adjacent to each other.”).
As to claim 4, Ikeda further teaches the structure of claim 1, wherein
the base structure (base region 17 + 23, Ikeda, Fig. 1 ) includes a substantially T-shaped base material having a base contact thereon (surface between 17 and 23, Ikeda Fig. 1).
As to claim 5, Ikeda further teaches the structure of claim 1, wherein
the bounding structure (6b, Ikeda, Fig. 1) is free of conductive contacts thereon (an insulating film is not conductive, (col 7, lines10-11 lines) “A filling material 6b made of a polycrystalline silicon film or an insulating film” )
As to claim 6, Ikeda further teaches the structure of claim 1, wherein
the bounding structure (6b, Ikeda, Fig.1) is on a semiconductor material (layer 2, n-type Fig. 2”) having a same conductivity type as the E/C layer (n type).
As to claim 8, Ikeda further teaches a structure comprising:
a first emitter/collector (E/C) layer (1st emitter region 20, Ikeda, Fig. 1) over a substrate (substrate 1, Ikeda, Fig. 1)
a base structure (base region 20 + T shaped base interconnection layer 22, Ikeda, Fig. 1) over the substrate (substrate 1, Ikeda, Fig. 1)
and adjacent a first horizontal end of the first E/C layer (1st emitter region 17 + 23, Ikeda, Fig. 1), wherein the base structure (base structure 20 + 22) includes a base material ((col 10 lines 30-31, polycrystalline silicon film 20 is an interlayer insulating film) + (col 10 lines 31-33, an emitter interconnection layer 22))
a bounding structure (bounding structure gate electrode 11 + 12) over the substrate (substrate 1, Ikeda, Fig. 1) and adjacent the first horizontal end of the first E/C layer (1st emitter region 17 + 23, Ikeda, Fig. 1), wherein
the bounding structure (bounding structure gate electrode 11 + 12) includes a gate conductor (col 11 lines 6-8 “gate electrode 11 made of polycrystalline silicon films 11a and 11b both including n type impurity”)
having a different composition from the base material ; and
a spacer (sidewall insulating film 12) between the first E/C layer (1st emitter region 17 + 23, Ikeda, Fig. 1) and the bounding structure (bounding structure gate electrode 11 + 12).
(Regarding claim 8, base material ((col 10 lines 30-31, polycrystalline silicon film 20 is an interlayer insulating film) + (col 10 lines 31-33, an emitter interconnection layer 22)) differs from (polycrystalline silicon films 11a and 11b both including n type impurity”)
As to claim 9, Ikeda further teaches the structure of claim 8, wherein
the E/C layer (emitter region 20, Ikeda, Fig. 1) is within a first bipolar transistor and has a first conductivity type (col 4, lines 33-36, “The bipolar transistor includes a collector layer of a first conductivity type, an external base layer of the second conductivity type, an intrinsic base layer of the second conductivity type, and an emitter layer of the first conductivity type.”)
As to claim 10, Ikeda further teaches the structure of claim 9, wherein
the bounding structure (bounding structure gate electrode 11 + 12, Fig 1) is horizontally between the first bipolar transistor (Annotated 1st bipolar transistor, Ikeda, Fig. 1) and a second bipolar transistor, the second bipolar transistor (Annotated 2nd bipolar transistor, Ikeda, Fig. 1) having an additional E/C layer (additional E/C layer 24 + 5 as the collector ) of the first conductivity type.
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As to claim 11, Ikeda further teaches the structure of claim 9, wherein
the bounding structure (bounding structure gate electrode 11 + 12, Fig 1, col 11 lines 6-8 “a gate electrode 11 made of polycrystalline silicon films 11a and 11b both including n type impurity”) is on a semiconductor material (layer 3, col 6 lines 27-28 “p type semiconductor substrate” ) having a different conductivity type from the E/C layer (n type).
As to claim 13, Ikeda further teaches the structure of claim 8, further comprising:
a second emitter/collector (E/C) layer (layers containing 24 + 5) over the substrate (1) and having a first horizontal end adjacent the base structure (22 + 20) such that the base structure is horizontally between the first E/C layer (layers containing 17 + 23) and the second E/C layer (layers containing 24 + 5); and
an additional bounding structure (bounding structure 6b, Ikeda, Fig. 1) over the substrate (1) and adjacent a second horizontal end of the second E/C layer (layer containing 24 + 5), wherein
the additional bounding structure ((bounding structure 6b, Ikeda, Fig. 1) includes a base material free of conductive contacts thereon.(Insulating films are not conductive, col 7 lines 9-13 “ An insulating film 6a is formed along the surface of element isolation trench 6. A filling material 6b made of a polycrystalline silicon film or an insulating film is filled in a region surrounded by insulating film 6a”.
As to claim 14, Ikeda further teaches the structure of claim 13, wherein
the additional bounding structure (6b) is horizontally between the second E/C layer (layer containing 24 + 5) and a trench isolation (TI) layer (7).
As to claim 15, Ikeda further teaches the structure of claim 14, wherein
the TI layer (7) is horizontally between the additional bounding structure (6b) and a metal oxide semiconductor field effect transistor (MOSFET) structure (Annotated MOSFET structures, Ikeda Fig. 1).
As to claim 16, Ikeda further teaches a method comprising:
providing a substrate (1) ; (col 8 lines 6-9) “FIG. 2, an n.sup.+ buried layer 2 is formed in a bipolar transistor formation region and a P channel MOS transistor formation region on a p type semiconductor substrate 1.”) and
forming a bipolar junction transistor including at least: (col 6, lines 23-26, Ikeda, Fig. 1 “Referring to FIG. 1, in a semiconductor device according to a first embodiment, an NPN bipolar transistor, a P channel MOS transistor and an N channel MOS transistor are formed adjacent to each other.”).
a first emitter/collector (E/C) layer (1st emitter region 20, Ikeda, Fig. 1) on the substrate (1);
a base structure (base region (17) + T shaped base interconnection layer (23), Ikeda, Fig. 1, col 7, lines 20-23, ”A base interconnection layer 23 is formed to electrically contact to base extraction electrode layer 17 via another contact hole.”) on the semiconductor layer (layer 3) and adjacent a first horizontal end of the first E/C layer;
a bounding structure (bounding structure 6b, Ikeda, Fig. 1) over the semiconductor layer (layers 2- n type/ and layer 3 , col 8 lines 21 “A p.sup.- layer 3 is formed”) and adjacent a second horizontal end of the first E/C layer, (1st emitter region 20, Ikeda, Fig. 1) wherein
the bounding structure includes a base material (base material of component 6b); and
a spacer between the first E/C layer (20) and the bounding structure (6b).
As to claim 17, Ikeda further teaches the method of claim 16, further comprising
forming a trench isolation layer (col 8 lines 16-17 “An element isolation insulating film 7 is formed”) in the semiconductor layer (layers n type 2 /layer 3 , col 8 lines 21 “A p.sup.- layer 3 is formed”), wherein
the bounding structure (Fig. 1, 6b) and the first E/C layer (Fig. 1,20) are formed on the semiconductor layer (Fig. 1,layer 2) so that the bounding structure is horizontally between the first E/C layer (Fig. 1,20) and the TI layer (Fig. 1,7).
As to claim 18, Ikeda further teaches the method of claim 17, further comprising
forming a field effect transistor (FET) structure adjacent the TI layer (Fig. 1,7), wherein the TI layer is horizontally between the bounding structure (Fig. 1, 6b) and the FET structure. (col 6, lines 23-26, Ikeda, Fig. 1 “Referring to FIG. 1, in a semiconductor device according to a first embodiment, an NPN bipolar transistor, a P channel MOS transistor and an N channel MOS transistor are formed adjacent to each other.”).
As to claim 19, the method of claim 16, wherein
the bounding structure (Fig. 1,6b) is formed on a semiconductor material (Fig. 1, layer 2-n type) having a same conductivity type as the E/C layer (n type).
As to claim 20, the method of claim 16, further comprising:
forming a second emitter/collector (E/C) layer (col 7 lines 24-26 “A collector interconnection layer 24 is formed to electrically contact to n. sup.+ collector extraction layer 5 via another contact hole.) over the substrate (1) and
having a first horizontal end adjacent the base structure (Fig. 1, 17 + 23) such that the base structure is horizontally between the first E/C layer (Fig. 1, 20) and the second E/C layer (Fig. 1, 24 + 5); and
forming an additional bounding structure (Fig 1, 11) over the substrate (Fig. 1, 1) and adjacent a second horizontal end of the second E/C layer (Fig. 1, 24 + 5), wherein
the additional bounding structure (Fig 1, 11 + 12) includes a gate conductor (gate electrode 11) having a different composition from the base material (material of base structure 17 + 23)
(Regarding claim 20 See that (col 11 lines 6-8 “gate electrode 11 made of polycrystalline silicon films 11a and 11b both including n type impurity” and insulating film 12) differs from (polycrystalline silicon film 17.))
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. All obviousness rationales stated below are rationales that would have been obvious prior to the earliest effective filing date of the application.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda et al. (US 5471083) herein referred to as Ikeda.
As to claim 7, the structure of claim 1, further comprising:
a second emitter/collector (E/C) (duplicate parts obvious) layer on the substrate (substrate 1, Ikeda, Fig. 1), and having
a first horizontal end adjacent the base structure (base structure 17 + 23, Ikeda Fig. 1) such that
the base structure (base structure 17 + 23, Ikeda Fig. 1) is horizontally between the first E/C layer (Annotated 1st emitter region 20, Ikeda, Fig. 1) and the second E/C layer (Annotated 2nd emitter region 20, Ikeda, Fig. 1); and
an additional bounding structure (additional bounding structure gate electrode 11) over the substrate (substrate 1, Ikeda, Fig. 1) and adjacent a second horizontal end of the second E/C layer (duplicate part obvious ) wherein
the additional bounding structure (additional bounding structure gate electrode 11) includes a gate conductor having a same doping type as, and a different composition from, the base material. (col 11 lines 6-8 “gate electrode 11 made of polycrystalline silicon films 11a and 11b both including n type impurity”)
(Regarding claim(s) 7, Ikeda does not appear to expressly disclose " a second emitter/collector (E/C)"
However, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, that the Ikeda semiconductor device includes a plurality of field effect transistors and a bipolar transistors so as to be used in electronic circuits and projects. It has been held that “mere duplication of parts has no patentable significance unless a new and unexpected result is produced” (See MPEP 2144.04(VI)(B)).)
As to claim 12, Ikeda further teaches the structure of claim 11, further comprising:
a base contact (where 17 meets 7) on the base structure (17 + 23);
an E/C contact (where 17 meets 23) on the first E/C layer (17) ; and
a gate contact (where 11 meets 5) on the bounding structure (11), wherein
a (obvious) voltage bias of the gate contact controls conductivity through the semiconductor material (layer 3).
(Regarding claim 3, Ikeda discloses the semi…elements of claim 11 as discussed above, and further discloses the elements of claim 12. However, Ikeda does not appear to expressly disclose " voltage bias of the gate contact controls"
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make include a voltage bias of the gate contact controls in the Ikeda device because voltage bias must be applied to a gate contact to control the conductivity of a transistor channel, switching it between on and off states or setting the operating point for analog circuits so as to use an industrially tested and accepted device.)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN SHAW MUSLIM whose telephone number is (571)270-0071. The examiner can normally be reached Mon-Fri 7 am - 4 pm.
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/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897