Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18506137 filed on 11/10/2023.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election with traverse of claims 1-5, 8-16 in the reply filed on 4/30/2026 is acknowledged.
Applicants argument with respect to species I encompassing Figs. 1, 16, 39 is acknowledged.
Allowable subject matter
Claims 10-12 are objected to as being dependent upon a rejected base claim (independent claim 1), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: The closest prior art known to the Examiner is listed on the PTO 892 forms of record.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Park et al. (US 2019/0267440).
With respect to dependent claims 10-12, the cited prior art does not anticipate or make obvious, inter alia, the step of: “wherein the valley portion comprises a first portion extending in a first direction and a second portion extending in a second direction, wherein the at least one valley portion opening is formed in plurality in the second portion, and wherein a valley portion opening through which first scan lines disposed adjacent to each other along the first direction is connected is different from a valley portion opening through which light emission control lines disposed adjacent to each other along the first direction is connected”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 8-9, 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2019/0267440).
Regarding independent claim 1, Park et al. teach a light emitting display device comprising
a display area (Fig.1A, element DA, paragraph 0055), the display area comprising:
a plurality of pixel circuit portions (Fig. 4, elements PC1, PC2, paragraph 0088), a plurality of light emitting diodes (Figs. 1-4 , element OLED, paragraph 0055) electrically connected to the plurality of pixel circuit portions, respectively, and
a valley portion (Figs. 4, 13, element VA1 & VA2, paragraph 0089, 0189) that is disposed in the display area, surrounds at least one of the plurality of pixel circuit portions to partition the plurality of pixel circuit portions into a plurality of regions (Fig. 4), and includes at least one valley portion opening (Fig. 4 discloses wirings crossing through valley portion and Fig. 13 discloses valley opening).
Regarding claim 2, Park et al. teach wherein each of the plurality of pixel circuit portions comprises a plurality of conductive layers (Fig. 13 elements G2, GG, paragraph 0073, 0078), a semiconductor layer (Fig. 13 elements A1, paragraph 0114), and a plurality of insulating layers (Fig. 13 elements 112, 113, paragraph 0091), and wherein the valley portion is a portion of the plurality of insulating layers in which at least one of the plurality of insulating layers is removed (Fig. 13) and filled with an organic material (Fig. 13 elements 161, paragraph 0089).
Regarding claim 3, Park et al. teach wherein the plurality of light emitting diodes (Fig. 13, element OLED) are disposed on the plurality of pixel circuit portions.
Regarding claim 4, Park et al. teach wherein the valley portion comprises a first portion extending in a first direction and a second portion extending in a second direction (Fig. 4 discloses X and Y direction), and wherein the at least one valley portion opening is disposed in the second portion (Figs. 4 & 13).
Regarding claim 8, Park et al. teach wherein each of the plurality of pixel circuit portions comprises a plurality of wirings (Figs. 4 & 13, element 140 comprising 141/142/143/144/145, paragraph 0138), a plurality of transistors (Fig. 3, elements T1-T7, paragraph 0069), and a storage capacitor (Fig. 3, element Cst, paragraph 0069), and wherein at least one of the plurality of wirings directly connecting adjacent pixel circuit portions is connected through the at least one valley portion opening (Figs. 4, 13).
Regarding claim 9, Park et al. teach wherein the plurality of transistors included in the each of the plurality of pixel circuit portions comprise a first transistor (Fig. 3, element T1), a second transistor (Fig. 3, element T2), a third transistor (Fig. 3, element T3), a fourth transistor (Fig. 3, element T4), a fifth transistor (Fig. 3, element T5), and a sixth transistor (Fig. 3, element T6), wherein the plurality of wirings comprise: a first scan line (Figs. 3-4, element 121) connected to a gate electrode of the second transistor (Fig. 3); a second scan line (Figs. 3-4, element 122) connected to a gate electrode of the third transistor; an initialization control line (Figs. 2-3, element 131) connected to a gate electrode of the fourth transistor; and a light emission control line (Fig. 3, element 123) connected to a gate electrode of the fifth transistor and a gate electrode of the sixth transistor, and wherein the at least one of the plurality of wirings directly connecting the adjacent pixel circuit portions through the at least one valley portion opening is one of the first scan line, the second scan line, the initialization control line, and the light emission control line (Figs. 4, 13).
Regarding claim 14, Park et al. teach further comprising a metal layer (Fig. 4 discloses metal wiring) that is provided in a lower portion of the first transistor (Fig. 4, element T1) and overlaps a channel of the first transistor, wherein the metal layer extends while overlapping the valley portion.
Regarding claim 15, Park et al. teach wherein the polycrystalline semiconductor included in the first transistor, the second transistor, the fifth transistor, and the sixth transistor is formed as a first semiconductor layer (Figs. 10-13), and wherein the first semiconductor layer comprises a portion formed in common with an adjacent first semiconductor layer (Figs. 10-13, the channel regions for the transistors are formed from a common layer as disclosed in the figures).
Regarding claim 16, Park et al. teach wherein the portion formed in common among the first semiconductor layer overlaps with the valley portion in a plan view (Figs. 4, 10-13).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2019/0267440).
Regarding claim 5, Park et al. teach wherein the at least one valley portion opening disposed in the second portion is formed in a plurality (Fig. 13 discloses openings for VA1 & VA2, furthermore, duplication of the openings would be obvious to one of ordinary skill in the art) and wherein at least two valley portion openings are disposed on a line extending along the first direction.
Regarding claim 13, Park et al. teach wherein the first transistor, the second transistor, the fifth transistor, and the sixth transistor comprise a polycrystalline semiconductor (paragraph 0107), and wherein the third transistor and the fourth transistor comprise an oxide semiconductor (Before the effective filling date of the invention it would have been obvious to one having ordinary skill in the art to select a known oxide semiconductor material, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAHED AHMED/
Primary Examiner, Art Unit 2813
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