DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to 07/15/2026 Amendment.
Claims 10-15, 30-43 are pending and examined. Claims 1-9, 16-29 have been cancelled.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 10, 12-13, 30, 32-33, 35-39, 41-42 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 6,903,967 to Mathew et al. (hereafter Mathew).
Regarding independent claim 10, Mathew teaches a method for operating a memory cell, comprising:
providing a multi-time programmable memory cell comprising:
a source region (FIG. 9: source/drain region 303);
a drain region (FIG. 9: drain/source region 305);
a channel region connected between the source region and the drain region (FIG. 10: channel region 105), wherein the channel region has a first sidewall (FIG. 10: left wall of channel region 105), a second sidewall (FIG. 10: right wall of channel region 105) and a top surface connecting the first sidewall and the second sidewall (FIG. 10: top surface of channel 105);
a first storage node formed on the first sidewall of the channel region (FIGS. 17: e.g. charge storage location 1709);
a second storage node formed on the second sidewall of the channel region (FIG. 17: e.g. charge storage location 1713), wherein the first storage node and the second storage node are connected over the top surface of the channel region (FIG. 12: charge storage layer 1203, which runs continuously from left to right including the top surface, see 5:66-6:9);
a first control gate electrode layer disposed on the first storage node (FIG. 17: gate structure 1503); and
a second control gate electrode layer disposed on the second storage node (FIG. 17: gate structure 1505); and
injecting electrons to the first storage node by applying a first control voltage on the first control gate electrode layer while applying a second control voltage to the second contro1 gate electrode layer, wherein the first control voltage is different from the second control voltage (FIGS. 18-19: storing charge to charge storage location 1713 by applying VPP to WL0, and VSS to WL1).
Regarding dependent claim 12, Mathew teaches wherein injecting electrons to the first storage node further comprises: applying a source voltage on the source region (FIG. 19: applying BL2 ); and applying a drain voltage on the drain region, wherein the first control voltage is a positive voltage (FIGS. 18-19: applying VPP to WL0), the second control voltage and the source voltage are about 0V (FIGS. 18-19: applying VSS to WL1 and BL2), and the drain voltage is a positive voltage (FIGS. 18-19: applying VPP/2 to BL1).
Regarding dependent claims 13, Mathew teaches removing electrons from the first storage node by applying a third control voltage on the first control gate electrode layer (FIGS. 18-19: applying -VPP to WL0) while applying a fourth control voltage to the second control gate electrode layer (FIGS. 18-19: applying VSS to WL1), wherein the third control voltage is different from the fourth control voltage.
Regarding independent claim 30, Mathew teaches a method for operating a memory cell, comprising:
providing a memory cell comprising:
a source region (FIG. 9: source/drain region 303);
a drain region (FIG. 9: drain/source region 305);
a channel region connected between the source region and the drain region (FIG. 10: channel region 105), wherein the channel region has a first sidewall (FIG. 10: left wall of channel region 105), a second sidewall (FIG. 10: right wall of channel region 105) and a top surface connecting the first sidewall and the second sidewall (FIG. 10: top surface of channel 105);
a first storage node formed on the first sidewall of the channel region (FIGS. 17: e.g. charge storage location 1709);
a second storage node formed on the second sidewall of the channel region (FIG. 17: e.g. charge storage location 1713), wherein the first storage node and the second storage node are connected over the top surface of the channel region (FIG. 12: charge storage layer 1203, which runs continuously from left to right including the top surface, see 5:66-6:9);
a first control gate electrode layer disposed on the first storage node (FIG. 17: gate structure 1503); and
a second control gate electrode layer disposed on the second storage node (FIG. 17: gate structure 1505);
operating the first storage node by applying a first control voltage on the first control gate electrode layer while applying a second control voltage to the second control gate electrode layer, wherein the first control voltage is different from the second control voltage (FIGS. 18-19: storing charge to charge storage location 1713 by applying VPP to WL0, and VSS to WL1); and
operating the second storage node by applying the first control voltage on the second control electrode layer while applying the second control voltage to the first control gate electrode layer (FIGS. 18-19: storing charge to charge storage location 1711 by applying VPP to WL1, and VSS to WL0).
Regarding dependent claims 32-33, see rejection applied to claims 12-13 above.
Regarding independent claim 35, Mathew teaches a method for operating a memory cell, comprising:
providing a memory cell comprising:
a source region (FIG. 9: source/drain region 303);
a drain region (FIG. 9: drain/source region 305);
a channel region connecting the source region and the drain region (FIG. 12: channel region 1105), wherein the channel region has a first sidewall (FIG. 12: left wall of channel region 1105), a second sidewall (FIG. 12: right wall of channel region 1105) and a top surface connecting the first sidewall and the second sidewall (FIG. 10: top surface of channel 1105);
a first gate dielectric layer disposed on the channel region (FIG. 12: dielectric layers 1107);
a continuous storage gate electrode layer disposed on the first gate dielectric layer (FIG. 12: charge storage layer 1203, which runs continuously from left to right including the top surface, see 5:66-6:9);
a first control gate electrode layer disposed on the storage gate electrode layer, wherein the first gate control gate layer faces the first sidewall of the channel region (FIG. 15: gate structure 1505); and
a second control gate electrode layer disposed on the storage gate electrode layer, wherein the second gate control gate layer faces the second sidewall of the channel region (FIG. 15: gate structure 1503), and the first control gate electrode layer and the second control gate electrode layer are electrically isolated from each other (as shown in FIG. 15); and
applying a first control voltage to the first control gate electrode layer; and applying a second control voltage to the second control gate control gate electrode layer, wherein the first control voltage is different from the second control voltage (FIGS. 18-19: storing charge to charge storage location 1713 by applying VPP to WL0, and VSS to WL1).
Regarding dependent claim 36, Mathew teaches wherein the memory cell includes a first bit and a second bit, the first bit comprises a first portion of the storage gate electrode layer disposed between the first control gate electrode layer and the first sidewall of the channel region (FIG. 17: charge storage location 1709/1711), and the second bit comprises a second portion disposed between the second control gate electrode layer and the second sidewall of the channel region (FIG. 17: charge storage location 1713/1715).
Regarding dependent claim 37, Mathew teaches wherein the storage gate electrode layer further comprises: a top portion disposed over the top surface of the channel region, and the top portion connects the first portion and the second portion (FIG. 15: conformal layer 1403).
Regarding dependent claim 38, Mathew teaches wherein the memory cell further comprises: a second gate dielectric layer disposed between the storage gate electrode layer and the first control gate electrode layer (FIG. 15: conformal layer 1403).
Regarding dependent claim 39, Mathew implicitly wherein the first gate dielectric layer and the second gate dielectric layer include different material (FIG. 14: layer 1403 is of control dielectric, which maybe different from layer 1107 of regular dielectric).
Regarding dependent claim 41, Mathew implicitly teaches wherein the channel region is a p-type channel (when the positive voltage is used for program as shown in FIG. 19).
Regarding dependent claim 42, Mathew implicitly teaches wherein the channel region is a n-type channel (when the negative voltage is used for program as shown in FIG. 21).
Claims 35, 40 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 7,927,951 to Kim et al. (hereafter Kim).
Regarding independent claim 35, Kim teaches a method for operating a memory cell, comprising:
providing a memory cell comprising:
a source region (FIG. 5E: source 10as);
a drain region (FIG. 5E: drain 10ad);
a channel region connecting the source region and the drain region (FIG. 5E: channel region 10ac), wherein the channel region has a first sidewall (FIG. 3: left wall of channel WCH1), a second sidewall (FIG. 3: right wall of channel WCH2) and a top surface connecting the first sidewall and the second sidewall (FIG. 5E: top surface of channel 10ac);
a first gate dielectric layer disposed on the channel region (FIG. 5E: tunnel insulation layer 30);
a storage gate electrode layer disposed on the first gate dielectric layer (FIG. 5E: storage charge layer 40);
a first control gate electrode layer disposed on the storage gate electrode layer, wherein the first gate control gate layer faces the first sidewall of the channel region (FIG. 5F: first control gate 61); and
a second control gate electrode layer disposed on the storage gate electrode layer, wherein the second gate control gate layer faces the second sidewall of the channel region (FIG. 5F: second control gate 62), and the first control gate electrode layer and the second control gate electrode layer are electrically isolated from each other (as shown in FIG. 5F); and
applying a first control voltage to the first control gate electrode layer; and applying a second control voltage to the second control gate control gate electrode layer, wherein the first control voltage is different from the second control voltage (FIG. 7A: e.g. storing charge to first charge storage pattern by applying 12V to first control gate 61 and 0V to second control gate 62).
Regarding dependent claim 40, Kim teaches wherein the first gate dielectric layer extends along a bottom surface of the storage gate electrode layer and disposed between the storage gate electrode layer and the first control gate electrode layer (FIG. 5E: see tunnel insulation layer 30).
Allowable Subject Matter
Claims 11, 14-15, 31, 34, 43 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to dependent claim 11: wherein injecting electrons to the first storage node further comprises: applying a source voltage on the source region; and applying a drain voltage on the drain region, wherein the first control voltage is a positive voltage, and the second control voltage, the source voltage and drain voltage are about 0V.
With respect to dependent claim 14: wherein removing electrons from the first storage node comprising: applying a source voltage on the source region; and applying a drain voltage on the drain region, wherein the third control voltage is a negative voltage, and the fourth control voltage, the source voltage and drain voltage are about 0V.
With respect to dependent claim 15: wherein removing electrons from the first storage node comprising: applying a source voltage on the source region; and applying a drain voltage on the drain region, wherein the third control voltage is a positive voltage, the source voltage and drain voltage are positive voltages greater than the third control voltage, and the fourth control voltage is about 0V.
With respect to dependent claim 31: wherein operating the first storage node further comprises: applying a source voltage on the source region; and applying a drain voltage on the drain region, wherein the first control voltage is a positive voltage, and the second control voltage, the source voltage and drain voltage are about 0V.
With respect to dependent claim 34: applying a source voltage on the source region; and applying a drain voltage on the drain region, wherein the third control voltage is a negative voltage, and the fourth control voltage, the source voltage and drain voltage are about 0V.
With respect to dependent claim 43: wherein the channel region comprises two or more semiconductor fins.
Response to Arguments
Applicant’s arguments with respect to claims 1, 30 and 35 have been considered but are not persuasive.
Mathew clearly teaches, in FIG. 12 and col. 5 ll. 66 to col. 6 ll. 9, a charge storage layer 1203 run continuously from left to right. The charge storage layer 1203 comprises first storage charge area on the left and second storage charge area on the right with the semiconductor structure portion 1105 in between.
Claims 10-15, 30-43 maintain rejected for the reason set forth above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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August 20, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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