Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-14 in the reply filed on 04/23/2026 is acknowledged.
Claims 15-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/23/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation "a second connection electrode". There is insufficient antecedent basis for this limitation in the claim. It appears as if the “second connection electrode” is following the “first connection electrode” which was introduced in claim 5. However, claim 11 doesn’t depend on claim 5. It is unclear if this second connection electrode is supposed to be different and in addition to the first connection electrode or if the device as claimed in claim 11 can only have one connection electrode called the second connection electrode. In an effort for compact prosecution, the claims will attempt to be examined as if second connection electrode is a different connection electrode then first connection electrode, however, regardless, appropriate action is still needed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-9, 11, and 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by United States Patent Application Publication by Jeon et al. (US 20200395434 A1; Jeon).
Regarding claim 1, Jeon discloses a display apparatus comprising:
a substrate (110) having a display area (DA) in which display elements (PX) are arranged (Fig. 1, Where display elements PX are arranged in the display area DA all on the substrate 110);
a first thin-film transistor (T1) in the display area and comprising a first semiconductor layer (A1) and a first gate electrode (G1), the first semiconductor layer comprising an oxide semiconductor (Para. 92, “In an alternative embodiment, the first and second semiconductor layers A1 and A2 may include an oxide of at least one selected from In, Ga, Sn, Zr, V, Hf, Cd, Ge, Cr, Ti and Zn”) and the first gate electrode being insulated from the first semiconductor layer (Para. 93, “The first and second gate electrodes G1 and G2 are arranged over the first and second semiconductor layers A1 and A2 with a gate insulating layer 112 therebetween”); and
a first interlayer insulating layer (112) between the first semiconductor layer (A1) and the first gate electrode (G1) (Fig. 3, Where first interlayer insulating layer 112 is between first gate electrode G1 and first semiconductor layer A1),
wherein the first interlayer insulating layer on the first semiconductor layer has a first length in a first direction (Fig. 3, where we will call the first direction to be left to right in the figure, and the first length is the length of the first interlayer insulating layer left to right in Fig. 3),
wherein the first gate electrode on the first interlayer insulating layer has a second length in the first direction (Fig. 3, where we will call the first direction to be left to right in the figure, and the second length is the length of the first gate electrode left to right in Fig. 3), and
wherein the first length is greater than the second length (Fig. 3, As the first interlayer insulating layer tapers to the first gate insulating layer in the first direction. Therefore, the first length will be shorter for the first insulating layer 112 in the first direction then the length for the first gate electrode in the first direction). Examiner note, even though the upper edge of the first interlayer insulating layer and the lower edge of the first gate electrode are same length, that is not true for the whole of each layer.
Regarding claim 2, Jeon discloses the display apparatus of claim 1, further comprising a first gate insulating layer (113) covering the first gate electrode (Fig. 3, where first gate insulating layer 113 is covering the first gate electrode G1).
Regarding claim 3, Jeon discloses the display apparatus of claim 2, further comprising:
a bottom metal layer (BSM) on the substrate; and
a buffer layer (111b) on the bottom metal layer (Fig. 3, Where bottom metal layer BSM is on substrate 110 and buffer layer 111b is on bottom metal layer BSM).
Regarding claim 4, Jeon discloses the display apparatus of claim 3, and further comprising a second interlayer insulating layer (111b) directly on at least a portion of the buffer layer and defining a contact hole therein (The buffer layer is the combination of 111a and 111b, while the second interlayer insulating layer can be considered just 111a. Fig 3, also shows that the contact whole goes through the buffer layer which could be considered having the second interlayer insulating layer 111b defining the contact hole).
Regarding claim 5, Jeon discloses the display apparatus of claim 4, further comprising a first connection electrode (210) on the second interlayer insulating layer (Fig. 3, where the first connection electrode is on, albeit not directly, the second interlayer insulating layer 111b.)
Regarding claim 6, Jeon discloses the display apparatus of claim 5, wherein the first connection electrode is electrically connected to the bottom metal layer through a contact hole defined in the second interlayer insulating layer and the buffer layer (Fig. 3, Where the first connection electrode 210 is connected to the bottom metal layer at least electrically through the drain electrode D1. See Also Para. 126, “In such an embodiment, the pixel electrode 210 may connect the first drain electrode D1 to the first additional drain electrode D1′, and the source connection electrode CM′ may connect the first source electrode S1 to the first additional source electrode S1” and Para. 91, “The bias electrode BSM may be arranged between the first buffer layer 111a and the second buffer layer 111b. The bias electrode BSM may be arranged to overlap at least a portion of the first thin film transistor T1 and may be connected to the first drain electrode D1 of the first thin film transistor T1”).
Regarding claim 7, Jeon discloses the display apparatus of claim 3, further comprising:
a lower electrode (CE1) directly on the buffer layer (111b); and
an upper electrode (CE2) over the lower electrode (Fig. 3, where upper electrode CE2 is over lower electrode CE1),
wherein the upper electrode and the lower electrode form a capacitor (Para. 99, “In an embodiment, the second electrode CE2 of the storage capacitor Cst overlaps the first electrode CE1 and the first interlayer insulating layer 113 is disposed therebetween. In such an embodiment, the first interlayer insulating layer 113 may serve as a dielectric layer of the storage capacitor Cst”).
Regarding claim 8, Jeon discloses the display apparatus of claim 7, wherein the first gate insulating layer is between the lower electrode and the upper electrode (Fig. 3 and Para. 99, “In an embodiment, the second electrode CE2 of the storage capacitor Cst overlaps the first electrode CE1 and the first interlayer insulating layer 113 is disposed therebetween”).
Regarding claim 9, Jeon discloses the display apparatus of claim 3, further comprising a second gate electrode (G2) on the first gate insulating layer (Fig. 3, Where the second gate electrode G2 is disposed on the first gate insulating layer 113).
Regarding claim 11, Jeon discloses the display apparatus of claim 7, further comprising:
a second gate insulating layer (117) on the first gate insulating layer (113); and
a second connection electrode (CM’), a source electrode (S1), and a drain electrode (D1) on the second gate insulating layer (Fig. 3, Where all of the source electrode S1m drain electrode D1, and the second connection electrode CM’ are on the second gate insulating layer 117).
Regarding claim 13, Jeon discloses the display apparatus of claim 11, further comprising:
a first organic insulating layer (119 – Para. 109, “The pixel-defining layer 119 may include an organic material such as PI or HMDSO”) on the second connection electrode (Fig. 3); and
a third connection electrode (210) on the first organic insulating layer (Fig. 3, where the third connection electrode 210 is at least adjacent to the first organic insulating layer 119, which under broadest reasonable interpretation, could be considered on the first organic insulating layer”).
Regarding claim 14, Jeon discloses the display apparatus of claim 13, wherein the third connection electrode (210) is electrically connected to the source electrode or the drain electrode through a contact hole defined in the first organic insulating layer (Fig. 3, Where the third connection electrode 210 is Connected to the drain electrode D1 through the first organic connection layer).
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
United States Patent Application Publication by Yun et al. (US 20220165806 A1, Yun).
United States Patent Application Publication by Choi et al. (US 20170179164 A1, Choi).
Allowable Subject Matter
Claims 10 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 10, the prior art of record fails to either anticipate or as in an obvious combination “wherein the second gate electrode (G2) is electrically connected to the bottom metal layer through a contact hole defined in the first gate insulating layer and the buffer layer” along with the other limitations of the claim. The prior art does not teach having a second gate connected to the bottom metal layer and instead in the Jeon reference, the bottom metal layer is connected to the drain electrode through a via.
Regarding claim 12, Jeon discloses the display apparatus of claim 11,
wherein the source electrode and the drain electrode are electrically connected to the first semiconductor layer through contact holes defined in the first interlayer insulating layer (Para. 91 and Fig. 3)
However, the prior art of record fails to either anticipate or as in an obvious combination “wherein the second connection electrode is electrically connected to the upper electrode of the capacitor through a contact hole defined in the first interlayer insulating layer” along with the other limitations of the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J HIBBERT whose telephone number is (703)756-1562. The examiner can normally be reached Monday - Friday 10am-6pm EST.
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/DANIEL J HIBBERT/Examiner, Art Unit 2899
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