DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
Applicant's election with traverse of Invention I-B (claims 10-17) in the reply filed on 03/05/2026 is acknowledged. The traversal is based on Applicant’s amendments to claim 10 incorporating limitations corresponding to original claim 1, such that the previously identified combination-subcombination distinction is no longer applicable.
Applicant’s traversal is found persuasive, the restriction requirement between inventions I-A and I-B is currently withdrawn.
Priority
Applicant’s claim for the benefit of provisional application 63/508334 submitted on 06/15/2023 is acknowledged.
Information Disclosure Statement
Applicant is suggested/reminded to disclose relevant prior art(s) or other information that may be material to the patentability of the invention in a pending application. The prior art information must be submitted in the form of an information Disclosure Statement (“IDS”) (see MPEP 609 & 2001 and 37 CFR 1.56).
Claim Objections
Claims 1, 2, 4, 6, 10, and 21 are objected to because of the following informalities:
In claim 1, line 3, “interconnect structure being” should read --the interconnect structure being-- (emphasis added).
In claim 2, line 3, “that surrounds the first device region,” should read --that surrounds the first device region[[,]];-- (emphasis added).
In claim 4, line 6, “X is s number” should read --X is [[s]] a number-- (emphasis added).
In claim 6, line 2, “comprises dielectric layer having” should read --comprises a dielectric layer having--, line 3, “a plurality of contact pads each contact pad” should read --a plurality of contact pads, each contact pad --, and line 6, “having contacts pads forming” should read --having contact[[s]] pads forming-- (emphasis added).
In claim 10, line 30, “stitching conductor electrically connecting” should read --stitching conductor [[om]] electrically connecting-- (emphasis added).
In claim 21, lines 31-32, “the intermediate pattern further” should read --the intermediate metallization pattern further-- (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, and 8-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Debral et al. (US 2022/0293433; hereinafter ‘Debral’).
Regarding claim 1, Debral teaches a device (150, FIGS. 2A-2C, [0056]) comprising:
a semiconductor substrate (101, [0057], FIG. 2B);
an interconnect structure (120, [0057], FIG. 2B) on the semiconductor substrate (101), interconnect structure (120) being organized into a plurality of device regions (110, [0057], FIGS. 2A and 2B);
a first seal ring (left 122, FIG. 2A, [0056]; hereinafter ‘122L’) extending vertically through the interconnect structure (122L extending vertically through 120, FIG. 2B) in a first device region (left 110, FIGS. 2A and 2B; hereinafter ‘110L’);
second seal ring (right 122; hereinafter ‘122R’) extending vertically through the interconnect structure (122R extending vertically through 120) in a second device region (right 110; hereinafter ‘110R’); and
a first horizontally extending conductive line (130, [0057], FIGS. 2A and 2B) in the interconnect structure (120),
the first horizontally extending conductive line (130) electrically connecting a first metallization pattern (left end portion 169 of 130 including 132 and 135, [0060, 0063], FIGS. 2B and 2C; hereinafter ‘169L’) located within the first seal ring (122L) to a second metallization pattern (right end portion 169 of 130 including 132 and 135; hereinafter ‘169R’) located within the second seal ring (122R),
wherein the first horizontally extending conductive line (130) extends through the periphery of the first seal ring and the second seal ring (130 extends through the periphery of 122L and 122R).
Regarding claim 5, Debral teaches the device of claim 1, wherein
the interconnect structure (120, FIGS. 1A and 2A) is divided into M device regions (plurality of 110, [0052, 0054]), and
further comprising M seal rings (plurality of 122, [0054]),
each seal ring of the M seal rings (122) providing signal isolation to circuitry within the corresponding device region (122 surrounding corresponding 110 to maintain seal integrity between adjacent 110, [0043-0044, 0054]) and
further comprising M−1 horizontally extending conductive lines (plurality of 130 disposed between adjacent 110, such that the number of 130 is one less than the number of adjacent 110 interconnected thereby, FIG. 1A),
each horizontally extending conductive line (130) electrically connecting circuitry in one of the M device regions to circuitry in an adjacent one of the M device regions (130 electrically connecting adjacent 110, FIGS. 2A-2C).
Regarding claim 8, Debral teaches the device of claim 1, wherein the semiconductor substrate (101, FIG. 2B) and the interconnect structure (120) on the semiconductor substrate (101) are part of a bottom integrated circuit (chip structure 150 including 101 and 120, [0044, 0077-0078]).
Regarding claim 9, Debral teaches the device of claim 1,
wherein the semiconductor substrate (101, FIGS. 1A, 2B, and 12) includes a plurality of bottom integrated circuit regions (plurality of 110 of chip structure 150, FIG. 1A, [0052]) separated by scribe lines (129 in 125, FIGS. 2B and 12, [0060-0061]),
each bottom integrated circuit region (110, FIG. 12, [0082]) including
an interconnect structure (120, [0082]) organized into a plurality of device regions (120 organized into 110),
a plurality of seal rings (122, [0082]), and
a plurality of horizontally extending conductive line (130, [0082]) extending through adjacent seal ring (130 extending through adjacent 122).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable Debral (US 2022/0293433).
Regarding claim 2, Debral teaches the device of claim 1 wherein the first seal ring (122L in FIG. 2A) corresponds to comprises
a first conductor (135 of M4 in 162 of 122L, FIG. 2C, [0058, 0063]; hereinafter ‘135M4’) in a first layer (M4 of 134) of the interconnect structure (120), wherein the first conductor surrounds the first device region (135M4 surrounds 110L),
a second conductor (135 of M3 in 162 of 122L; hereinafter ‘135M3’) in a second layer (M3 of 134) of the interconnect structure (120), below the first layer (M4), wherein the second conductor surrounds the first device region (135M3 surrounds 110L); and
a third conductor (135 of M2 in 162 of 122L; hereinafter ‘135M2’) in a third layer (M2 of 134) of the interconnect structure (120), below the second layer (M3), wherein the third conductor surrounds the first device region (135M2 surrounds 110L).
Debral does not explicitly teach that the first conductor forms a closed polygon, the second conductor forms an open polygon and partially surrounds the first device region; and the third conductor forms a closed polygon.
Debral, however, discloses each die area 110 is surrounded by metallic seal 122, which is a split metallic seal structure (open polygon) or full seal structure (closed polygon) [0054].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Debral to obtain and achieve the device wherein the first conductor forms a closed polygon, the second conductor forms an open polygon and partially surrounds the first device region; and the third conductor forms a closed polygon as claimed, because selecting either open polygon seal structures or closed polygon seal structures depending upon the embodiment accommodates die-to-die routing and through seal interconnects between adjacent device regions while maintaining seal integrity [0043-0044, 0054, 0060]. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding claim 3, Debral teaches the device of claim 2, wherein the first horizontally extending conductive line (130, FIGS. 2A and 2B) is in the third layer of the interconnect structure (130 is formed in M2 of 120, FIG. 2C).
Regarding claim 4, Debral teaches the device of claim 2, wherein:
the interconnect structure (120) comprises N conductive layers (plurality of 134 including M1, M2, M3, and M4, FIG. 2C, [0063]); and
the first seal ring (122L) comprises
a stack of N-X conductors (135 in 162 of 122L selectively formed in conductive layers among M1 to M4; hereinafter ‘135C1’) forming N-X respective closed polygons (135C1 of 122L forming full seal structures, [0054]) that respectively surround the first device region (135C1 of 122L surrounds 110L), and
X conductors (135 in 162 of 122L selectively formed in other conductive layers among M1 to M4 except 135C1; hereinafter '135C2’) forming X respective open polygons (135C2 of 122L forming split seal structures) that respectively partially surround the first device region (135C2 of 122L partially surrounds 110L); and
wherein N is a number greater than or equal to three (N is four).
Debral does not explicitly teach that X is a number greater than or equal to one
Debral, however, discloses that metallic seal 122 is implemented as either split metallic seal structures of full seal structures depending upon the embodiment [0054].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Debral to obtain and achieve the device wherein X is a number greater than or equal to one as claimed, because selectively configuring a combination of conductive layers as either open polygon seal structures or closed polygon seal structures depending upon the embodiment accommodates die-to-die routing and through seal interconnects between adjacent device regions while maintaining seal integrity [0043-0044, 0054, 0060]. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable Debral (US 2022/0293433) in view of Debral et al. (US 2022/0199517; hereinafter ‘Debral517’).
Regarding claim 6, Debral teaches the device of claim 1, wherein:
a top layer of the interconnect structure (upper portion of 120, FIG. 2B) comprises
dielectric layer (182, [0059]) having a top surface (a top surface of 182) and
a plurality of contact pads (plurality of 141, [0059]) each contact pad of the plurality of contact pads (141) having a top surface (141 having a top surface)
that is level with the top surface of the dielectric layer (the top surface of 141 being coplanar with the top surface of 182, FIG. 2B); and
further comprising a first integrated circuit (IC, [0053]; hereinafter ‘110LIC’) on the first device region (110L), and
a second integrated circuit (IC, [0053]; hereinafter ‘110RIC’) on the second device region (110R).
Debral does not teach the device wherein the first integrated circuit having contacts pads forming respective metal bond interfaces with respective contact pads of the interconnect structure and the second integrated circuit having contacts pads forming respective metal bond interfaces with respective contact pads of the interconnect structure.
Debral517 teaches a device (100, FIG. 13B, [0083]) wherein
the first integrated circuit (the first integrated circuit disposed on 110A, [0061]; hereinafter ‘110AIC’) having contacts pads (119 electrically connected to 110AIC through 117, [0084]; hereinafter ‘119A’) forming respective metal bond (metal-metal bond, [0084]) interfaces with respective contact pads of the interconnect structure (119A forming respective metal-metal bond interfaces with corresponding 140 of 120, FIG. 13B) and
the second integrated circuit (the second integrated circuit disposed on 110B; hereinafter ‘110BIC’) having contacts pads (119 electrically connected to 110BIC through 117; hereinafter ‘119B’) forming respective metal bond (metal-metal bond) interfaces with respective contact pads of the interconnect structure (119B forming respective metal-metal bond interfaces with corresponding 140 of 120, FIG. 13B).
As taught by Debral517, one of ordinary skill in the art would utilize and modify the above teaching into Debral to obtain and achieve the device wherein the first integrated circuit having contacts pads forming respective metal bond interfaces with respective contact pads of the interconnect structure and the second integrated circuit having contacts pads forming respective metal bond interfaces with respective contact pads of the interconnect structure as claimed, because hybrid bonding using metal contact pads provides vertical interconnection between stacked integrated circuits and the interconnect structure, thereby enabling expanded package integration and stacked device scaling [0083-0084].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Debral517 in combination with Debral due to above reason
Regarding claim 7, Debral in view of Debral517 teaches the device of claim 6, Debral does not teach the device further comprising a fusion bond interface between the dielectric layer of the interconnect structure and a top dielectric layer of the first integrated circuit, and a fusion bond interface between the dielectric layer of the interconnect structure and a top dielectric layer of the second integrated circuit.
Debral517 teaches the device (wafer-on-wafer stacked die sets 100, FIG. 13B) further comprising
a fusion bond interface (oxide-oxide bond interface, [0084]) between the dielectric layer of the interconnect structure (oxide layer in 120, [0062]) and a top dielectric layer of the first integrated circuit (oxide layer on the backside of 101 corresponding to of 110A, [0084]), and
a fusion bond interface (oxide-oxide bond interface) between the dielectric layer of the interconnect structure (oxide layer in 120) and a top dielectric layer of the second integrated circuit (oxide layer on the backside of 101 corresponding to of 110B).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Debral to obtain and achieve the device further comprising a fusion bond interface between the dielectric layer of the interconnect structure and a top dielectric layer of the first integrated circuit, and a fusion bond interface between the dielectric layer of the interconnect structure and a top dielectric layer of the second integrated circuit as claimed, because hybrid bonding including oxide-oxide bond interfaces provides reliable bonding between stacked integrated circuits and the interconnect structure, thereby enabling expanded package integration and stacked device scaling [0084].
Claims 10, 12, 14-17, and 21 are rejected under 35 U.S.C. 103 as being unpatentable Debral517 (US 2022/0199517).
Regarding claim 10, Debral517 teaches a package (100, FIG. 13B, [0083]) comprising:
a bottom integrated circuit (IC) (the bottom IC disposed on 110 of 113, [0061, 0083]; hereinafter ‘110113’) including an interconnect structure (120 in 113, [0057]; hereinafter ‘120113’);
a first top IC (the first top IC disposed on 110A of 111; hereinafter ‘110A111’)
having contact pads (119 electrically connected to 110A111 through 117, [0084]; hereinafter ‘119A111’) forming metallic bond (metal-metal bond, [0084]) interfaces with respective contact pads of the bottom IC (119A111 forming respective metal-metal bond interfaces with corresponding 140 of 120113) and
having a first top dielectric layer (oxide layer on the backside of 101 corresponding to of 110A111, [0084]) forming a fusion bond (oxide-oxide bond interface, [0084]) interface with a top dielectric layer of the bottom IC (oxide layer in 120113, [0062]),
wherein a projection of an outer periphery of the first top IC (a projection of an outer periphery of 110A111) defines a first die region in the interconnect structure (a first die region in 120113; hereinafter ‘120A113’);
a second top IC (the second top IC disposed on 110B of 111; hereinafter ‘110B111’)
having contact pads (119 electrically connected to 110B111 through 117; hereinafter ‘119B111’) forming metallic bond (metal-metal bond) interfaces with respective contact pads of the bottom IC (119B111 forming respective metal-metal bond interfaces with corresponding 140 of 120113) and
having a second top dielectric layer (oxide layer on the backside of 101 corresponding to of 110B111) forming a fusion bond (oxide-oxide bond interface) interface with the top dielectric layer of the bottom IC (oxide layer in 120113),
wherein a projection of an outer periphery of the second top IC (a projection of an outer periphery of 110B111) defines a second die region in the interconnect structure (a second die region in 120113; hereinafter ‘120B113’);
a first seal ring (the combination of left 122B and left 122A in 120A113; hereinafter ‘122L113’) including:
a first conductor (a first portion of 122L113 in M_high; hereinafter ‘122L113_high’) in a top layer of the interconnect structure (M_high, [0063]), wherein the first conductor surrounds the first die region (122L113_high surrounds 120A113),
a second conductor (a first portion of 122L113 in M_low; hereinafter ‘122L113_low’) in a bottom layer of the interconnect structure (M_low), wherein the second conductor surrounds the first die region (122L113_low surrounds 120A113),
a third conductor (a third portion of 122L113 in M_mid; hereinafter ‘122L113_mid’) in an intermediate layer of the interconnect structure (M_mid), wherein the third conductor having three sides aligned to three respective sides of the first die region and being open along a side of the first die region that is closest to the second die region (122L113_mid having three sides aligned to three respective sides of 120A113 and being open along a side of 120A113 that is closest to the 120B113 to accommodate die-to-die routing 130, [0063]);
a second seal ring (the combination of right 122B and right 122A in 120B113; hereinafter ‘122R113’) including:
a fourth conductor (a fourth portion of 122R113 in M_high; hereinafter ‘122R113_high’) in the top layer of the interconnect structure (M_high), wherein the fourth conductor surrounds the second die region (122R113_high surrounds 120B113),
a fifth conductor (a fifth portion of 122R113 in M_low; hereinafter ‘122L113_low’) in the bottom layer of the interconnect structure (M_low), wherein the fifth conductor surrounds the second die region (122R113_low surrounds 120B113),
a sixth conductor (a sixth portion of 122R113 in M_mid; hereinafter ‘122R113_mid’) in the intermediate layer of the interconnect structure (M_mid), wherein the sixth conductor having three sides aligned to three respective sides of the second die region and being open along a side of the second die region that is closest to the first die region (122R113_mid having three sides aligned to three respective sides of 120B113 and being open along a side of 120B113 that is closest to the 120A113 to accommodate die-to-die routing 130); and
a stitching conductor (the third 136 in M_mid, [0063]; hereinafter ‘136-3’) in the intermediate layer of the interconnect structure (M_mid),
the stitching conductor (136-3) electrically connecting a first conductor (132 and 134 in 120A113; hereinafter ‘132/134A113’) in the first die region (120A113) to a second conductor (132 and 134 in 120B113; hereinafter ‘132/134B113’) in the second die region (120B113), and
extending through the respective peripheries of the first seal ring and the second seal ring by extending through respective open sides of the third conductor and the sixth conductor (136-3 extending through the respective peripheries of 122L113 and 122R113 by extending through respective open sides of 122L113_mid and 122R113_mid).
Debral517 does not explicitly teach that the first and fourth conductors form closed polygons, the second and fifth conductors form second closed polygons, the third and sixth conductors form first open polygons.
Debral517, however, disclosed that FEOL die areas 110 include combinations of full metallic seals 122B and partial metallic seals 122A, where partial metallic seals are provided along edges accommodating die-to-die routing 130 and full metallic seals are provided along edges where such routing is not intended [0053, 0060].
Debral517 further teaches that various combinations of full metallic seals and partial metallic seals is formed depending upon routing configuration and desired seal integrity [0053].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Debral517 to obtain and achieve the package wherein the first and fourth conductors form closed polygons, the second and fifth conductors form second closed polygons, the third and sixth conductors form first open polygons as claimed, because selective use of full metallic seal structures and partial metallic seal structures to accommodate through-seal routing while maintaining seal integrity [0053, 0060]. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding claim 12, Debral517 teaches the package of claim 10, wherein the stitching conductor (136-3, FIG. 13B) electrically connects at least one of the contact pads of the first top IC to at least one of the contact pads of the second top IC (136-3 of die-to-die rouging 130 electrically connects the dies, and the dies are vertically interconnected to 119A111 to 119B111 through 117, [0063, 0084]).
Regarding claim 14, Debral517 teaches the package of claim 10, wherein the closed polygon that surrounds the first die region comprises continuous line segments (FEOL die areas 110 include full metallic seals 122 are provided along edges where such routing is not intended [0053, 0060]).
Regarding claim 15, Debral517 teaches the package of claim 10, wherein the closed polygon that surrounds the first die region comprises at least one line segment that is discontinuous (FEOL die areas 110 include partial metallic seals 122 are provided along edges where such routing is not intended [0053, 0060]).
Regarding claim 16, Debral517 teaches the package of claim 10, wherein the first seal ring comprises a number of vertically arranged closed polygon structures (122L113 comprises 122L113_high and 122L113_low, [0053, 0060, 0063]), and the second seal ring comprises a second number of vertically arranged closed polygon structures (122R113 comprises 122R113_high and 122R113_low).
Regarding claim 17, Debral517 teaches the package of claim 10, further comprising:
N top ICs (multiple stacked dies 104 in scalable stacked dies sets 100, FIG. 13A, [0082]), each top IC having contact pads forming metallic bond interfaces with respective contact pads of the bottom IC and each top IC having a top dielectric layer forming a fusion bond interface with the top dielectric layer of the bottom IC (metal-metal bond interfaces and oxide-oxide bond interfaces, [0084]), wherein a projection of an outer periphery of each top die IC (outer peripheries of respective stacked dies 104) defines one of N die regions in the interconnect structure (corresponding die regions associated with 104 in 120, FIG. 13B, [0082-0083]), wherein the N top ICs includes the first top IC and the second top IC (including 104A and 104B corresponding respectively to 110A and 110B, FIG 13B, [0064]);
N seal rings (plurality of 122), each seal ring (122) including:
a conductor in the top layer of the interconnect structure and forming a closed polygon that surrounds the one of N die regions (corresponding portions of 122 in upper metal layers M_high forming closed conductive paths surrounding corresponding die regions associated with respective 104, [0053, 0069],
a conductor in the bottom layer of the interconnect structure, and forming a second closed polygon that surrounds the one of the N die regions (corresponding portions of 122 in lower metal layers M_low forming closed conductive paths surrounding corresponding die regions associated with respective 104, [0053, 0069]),
a conductor in the intermediate layer of the interconnect structure, and forming an open polygon (corresponding portions of 122 in intermediate metal layers M_mid including openings 123 for 130, [0063]), the open polygon having three sides aligned to three respective sides of the one of the N die regions and being open along a side of the first die region that is closest to an adjacent one of the N die regions (the portions of 122 in M_mid extending along corresponding sides of adjacent die regions except for one side open to accommodate 130),
wherein the N seal rings includes the first seal ring and the second seal ring (including 122 corresponding to FELO die areas 110A and 110B, FIG. 13B); and
N-1 stitching conductors (repeated 136 within 130 between adjacent 104, such that the number of 136 is one less than the number of adjacent 104 interconnected thereby, FIG. 1B),
each of the N-1 stitch conductors extending from within the one of the N die regions to within the adjacent one of the N die regions (136 extending between adjacent 110 corresponding to adjacent 104),
wherein N-1 stitching conductors includes the stitching conductor (including 136).
Regarding claim 21, Debral517 teaches a package (100, FIG. 13B, [0083]) comprising:
a plurality of active components (transistor, interconnects, ring oscillator, [0071]) on a bottom integrated circuit (IC) (the bottom IC disposed on 110 of 113, [0061, 0083]; hereinafter ‘110113’);
an interconnect structure (120 in 113, [0057]; hereinafter ‘120113’), over the bottom IC (110113),
the interconnect structure (120113) including a stack of dielectric layers (insulating interlayer dielectrics (ILDs) for multiple metal layers, [0062, 0063]) on the bottom IC (110113),
respective metallization layers (metal layers including M_high, M_mid, and M_low, [0063]; hereinafter ‘ML’) embedded within respective ones of the stack of dielectric layers (ML embedded within respective ones of ILDS), and
conductive vias (132, [0063]) electrically connecting vertically adjacent metallization layers (132 electrically connecting vertically adjacent ML);
a first top IC (the first top IC disposed on 110A of 111; hereinafter ‘110A111’)
having first top contact pads (119 electrically connected to 110A111 through 117, [0084]; hereinafter ‘119A111’) forming a metal-to-metal bond (metal-metal bond, [0084]) with first contact pads of the bottom IC (140 of 110A113, [0084]) and
having a first top dielectric layer (oxide layer on the backside of 101 corresponding to of 110A111, [0084]) forming a fusion bond (oxide-oxide bond interface, [0084]) with a top dielectric layer of the stack of dielectric layers (oxide layer in 120113, [0062]); and
a second top IC (the second top IC disposed on 110B of 111; hereinafter ‘110B111’)
having second top contact pads (119 electrically connected to 110B111 through 117; hereinafter ‘119B111’) forming a metal-to-metal bond (metal-metal bond) with second contact pads of the bottom IC (140 of 110B113) and
having a second top dielectric layer forming a fusion bond with the top dielectric layer of the stack of dielectric layers; and
wherein the interconnect structure (oxide layer on the backside of 101 corresponding to of 110B111) over the bottom IC (110113) also includes:
a top metallization pattern (a first portion of 122 in M_high of 113; hereinafter ‘122113_high’) in a top metallization layer of the interconnect structure (M_high, [0063]), the top metallization pattern (122113_high) forming a first pattern (122113_high in 110A; hereinafter ‘122L113_high’) having a perimeter (122L113_high having a perimeter, FIG. 1B) that is vertically aligned to a perimeter of the first top IC (the perimeter of 122L113_high is vertically aligned to the perimeter of 110A111, FIGS. 1B and 13B), the top metallization pattern (122113_high) also forming a second pattern (122113_high in 110B; hereinafter ‘122R113_high’) having a perimeter (122R113_high having a perimeter) that is vertically aligned to a perimeter of the second top IC (the perimeter of 122R113_high is vertically aligned to the perimeter of 110B111),
a bottom metallization pattern (a third portion of 122 in M_low of 113; hereinafter ‘122113_low’) in a bottom metallization layer of the interconnect structure (M_low), the bottom metallization pattern (122113_low) forming a third pattern (122113_low in 110A; hereinafter ‘122L113_low’) having a perimeter (122L113_low having a perimeter) that is vertically aligned to the perimeter of the first top IC (the perimeter of 122L113_low is vertically aligned to the perimeter of 110A111), the bottom metallization pattern (122113_low) also forming a fourth pattern (122113_low in 110B; hereinafter ‘122R113_low’) having a perimeter (122R113_low having a perimeter) that is vertically aligned to the perimeter of the second top IC (the perimeter of 122R113_low is vertically aligned to the perimeter of 110B111), and
an intermediate metallization pattern (a first portion of 122 in M_mid of 113; hereinafter ‘122113_mid’) in an intermediate layer of the interconnect structure (M_mid), the intermediate metallization pattern (122113_mid) forming a first pattern (122113_mid in 110A; hereinafter ‘122L113_mid’) having a perimeter (122L113_mid having a perimeter) that is vertically aligned to the perimeter of the first top IC (the perimeter of 122L113_mid is vertically aligned to the perimeter of 110A111) and having an open side (the right side of 122L113_mid) vertically aligned with a side of the first top IC (the right side of 122L113_mid and the right side of 110A111 are vertically aligned, FIG. 13B) that is closest to the second top IC (the right side of 110A111 is closest to 110B111), the intermediate metallization pattern (122113_low) also forming a second pattern (122113_mid in 110B; hereinafter ‘122R113_mid’) having a perimeter (122R113_mid having a perimeter) that is vertically aligned to the perimeter of the second top IC (the perimeter of 122R113_mid is vertically aligned to the perimeter of 110B111) and having an open side (the left side of 122R113_mid) vertically aligned with a side of the second top IC (the left side of 122R113_mid and the left side of 110B111 are vertically aligned) that is closest to the first top IC (the left side of 110B111 is closest to 110A111), the intermediate metallization pattern (122113_mid) also forming at least one conductive line (134 in M_mid, [0063]; hereinafter ‘134 mid’) extending from within the perimeter of the first pattern to within the perimeter of the second pattern (134 mid extending from the perimeter of the 122L113_mid to within the perimeter of the 122R113_mid), the intermediate pattern (122113_mid) further electrically connecting (122113_mid electrically connecting die-to-die rouging 130 including 132 through 110113, [0063, 0084]) a first conductor (left 132 in M_mid, [0063]; hereinafter ‘132L mid’) located within the first pattern (122L113_mid) to a second conductor (right 132 in M_mid; hereinafter ‘132R mid’) located within the second pattern (122R113_mid).
Debral517 does not explicitly teach that the first and second patterns of the top metallization pattern and the first and second patterns of the bottom metallization pattern form closed polygons and the first and second patterns of the intermediate metallization pattern form open polygons.
Debral517, however, disclosed that FEOL die areas 110 include combinations of full metallic seals 122B and partial metallic seals 122A, where partial metallic seals are provided along edges accommodating die-to-die routing 130 and full metallic seals are provided along edges where such routing is not intended [0053, 0060].
Debral517 further teaches that various combinations of full metallic seals and partial metallic seals is formed depending upon routing configuration and desired seal integrity [0053].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Debral517 to obtain and achieve the package wherein the first and second patterns of the top metallization pattern and the first and second patterns of the bottom metallization pattern form closed polygons and the first and second patterns of the intermediate metallization pattern form open polygons as claimed, because selective use of full metallic seal structures and partial metallic seal structures to accommodate through-seal routing while maintaining seal integrity [0053, 0060]. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Claims 11, 13, and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable Debral517 (US 2022/0199517) in view of Debral (US 2022/0293433).
Regarding claim 11, Debral517 teaches the package of claim 10, wherein the second intermediate layer (the fourth 134 of 130 in M_mid, FIG. 13B, [0063]; hereinafter ‘M_mid2’) further includes a second stitching conductor (the fourth 136 in M_mid, [0063]; hereinafter ‘136-4’), the second stitching conductor extending from the first die region to the second die region through the respective open sides (136-4 extending from 120A113 to 120B113 the through the respective peripheries of 122L113 and 122R113 by extending through respective open sides).
Debra517 does not teach the package wherein: the first seal ring further comprises a seventh conductor in a second intermediate layer, the seventh conductor forming a third open polygon, the third open polygon having three sides aligned to three respective sides of the first die region and being open along a side of the first die region that is closest to the second die region; the second seal ring further comprises an eighth conductor in the second intermediate layer, the eighth conductor forming a fourth open polygon, the fourth open polygon having three sides aligned to three respective sides of the second die region and being open along a side of the second die region that is closest to the first die region.
Debral teaches a package (150, FIGS. 2A-2C, [0056]) wherein:
the first seal ring (left 122, FIG. 2A, [0056]; hereinafter ‘122L’) further comprises
a seventh conductor (135 of M3 in 162 of 122L, FIG. 2C, [0058, 0063]; hereinafter ‘135LM3’) in a second intermediate layer (M3 of Mmid),
the seventh conductor having three sides aligned to three respective sides of the first die region and being open along a side of the first die region that is closest to the second die region (135LM3 having three sides aligned to three respective sides of the left 110 (hereinafter ‘110L’) and being open along a side of 110L that is closest to the right 110 (hereinafter ‘110R’) to accommodate die-to-die routing 130, FIGS. 2A and 2B, [0057, 0064]);
the second seal ring (right 122; hereinafter ‘122R’) further comprises
an eighth conductor (135 of M3 in 162 of 122R; hereinafter ‘135RM3’) in the second intermediate layer (M3 of Mmid),
the eighth conductor having three sides aligned to three respective sides of the second die region and being open along a side of the second die region that is closest to the first die region (135RM3 having three sides aligned to three respective sides of 110R and being open along a side of 110R that is closest to 110L to accommodate die-to-die routing 130).
Debral does not explicitly teach that the seventh and eight conductors form open polygons.
Debral, however, discloses each die area 110 is surrounded by metallic seal 122, which is a split metallic seal structure (open polygon) [0054].
As taught by Debral, one of ordinary skill in the art would utilize and modify the above teaching into Debral to obtain and achieve the package wherein: the first seal ring further comprises a seventh conductor in a second intermediate layer, the seventh conductor forming a third open polygon, the third open polygon having three sides aligned to three respective sides of the first die region and being open along a side of the first die region that is closest to the second die region; the second seal ring further comprises an eighth conductor in the second intermediate layer, the eighth conductor forming a fourth open polygon, the fourth open polygon having three sides aligned to three respective sides of the second die region and being open along a side of the second die region that is closest to the first die region as claimed, because selecting open polygon seal structures depending upon the embodiment accommodates die-to-die routing and through seal interconnects between adjacent device regions while maintaining seal integrity [0043-0044, 0054, 0060]. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Debral in combination with Debral517 due to above reason.
Regarding claim 13, Debral517 teaches the package of claim 10, wherein the interconnect structure (120113, FIG. 13B) comprises N layers (120113 comprises 3 layers including M_high, M_mid, and M_low).
Debral517 does not teach the package wherein the first seal ring comprises N-1 closed polygons arranged in a vertical stack and one open polygon vertically aligned to the N-1 closed polygons and interjacent a topmost one of the N-1 closed polygons and a bottommost one of the N-1 closed polygons.
Debral teaches a package (150, FIGS. 2A-2C, [0056]) wherein the first seal ring (left 122, FIGS. 2A-2C, [0056]; hereinafter ‘122L’) comprises N-1 layers arranged in a vertical stack (135 of M4 in 162 of 122L (135M4), 135 of M2 in 162 of 122L (135M2), and 135 of M1 in 162 of 122L (135M1) arranged in a vertical stack, FIG. 2C, [0058, 0063]), one layer (135 of M3 in 162 of 122L (135M3)) vertically aligned to the N-1 layers (135M3 vertically aligned to 135M1, 135M2, and 135M4) and interjacent a topmost one of the N-1 layers and a bottommost one of the N-1 layers (135M3 interjacent 135M4 and 135M1).
Debral does not explicitly teach that the N-1 layers form closed polygons and one layer forms an open polygon.
Debral, however, discloses each die area 110 is surrounded by metallic seal 122, which is a split metallic seal structure (open polygon) or full seal structure (closed polygon) [0054].
As taught by Debral, one of ordinary skill in the art would utilize and modify the above teaching into Debral to obtain and achieve the package wherein the first seal ring comprises N-1 closed polygons arranged in a vertical stack and one open polygon vertically aligned to the N-1 closed polygons and interjacent a topmost one of the N-1 closed polygons and a bottommost one of the N-1 closed polygons as claimed, because selecting either open polygon seal structures or closed polygon seal structures depending upon the embodiment accommodates die-to-die routing and through seal interconnects between adjacent device regions while maintaining seal integrity [0043-0044, 0054, 0060]. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Debral in combination with Debral517 due to above reason.
Regarding claim 22, Debral517 teaches the package of claim 21, wherein the interconnect structure (120113, FIG. 13B) comprises N metallization layers (120113 comprises 3 metallization layers including M_high, M_mid, and M_low), and a first seal ring (the combination of left 122B and left 122A in 120A113; hereinafter ‘122L113’) beneath the first top IC (122L113 beneath 110A111), a second seal ring (the combination of right 122B and right 122A in 120B113; hereinafter ‘122R113’) beneath the second top IC (122R113 beneath 110B111).
Debral517 does not teach the package wherein the interconnect structure comprises N-X closed polygons and X open polygons forming a first seal ring, N-X other closed polygons, and X other open polygons to form a second seal ring.
Debral teaches a package (150, FIGS. 2A-2C, [0056]) wherein the interconnect structure (120, [0057], FIG. 2B) comprises N-X layers (135 of M4 in 162 of 122L (135M4), 135 of M2 in 162 of 122L (135M2), and 135 of M1 in 162 of 122L (135M1) arranged in a vertical stack, FIG. 2C, [0058, 0063]) and X layers (135 of M3 in 162 of 122L (135M3)) forming a first seal ring (left 122, FIGS. 2A-2C, [0056]; hereinafter ‘122L’), N-X other layers (135 of M4 in 162 of 122R (135M4), 135 of M2 in 162 of 122R (135M2), and 135 of M1 in 162 of 122R (135M1) arranged in a vertical stack), and X other layers (135 of M3 in 162 of 122R (135M3)) to form a second seal ring (right 122; hereinafter ‘122R’).
Debral does not explicitly teach that the N-X layers form closed polygons and X layer forms an open polygon.
Debral, however, discloses each die area 110 is surrounded by metallic seal 122, which is a split metallic seal structure (open polygon) or full seal structure (closed polygon) [0054].
As taught by Debral, one of ordinary skill in the art would utilize and modify the above teaching into Debral to obtain and achieve the package wherein the interconnect structure comprises N-X closed polygons and X open polygons forming a first seal ring, N-X other closed polygons, and X other open polygons to form a second seal ring as claimed, because selecting either open polygon seal structures or closed polygon seal structures depending upon the embodiment accommodates die-to-die routing and through seal interconnects between adjacent device regions while maintaining seal integrity [0043-0044, 0054, 0060]. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Debral in combination with Debral517 due to above reason.
Regarding claim 23, Debral517 teaches the package of claim 21, but does not teach the package wherein the bottom metallization pattern, the intermediate metallization pattern, and the bottom metallization pattern, collectively, are configured to reduce signal interference between the first top IC and the second top IC, relative to a level of signal interference in the absence of the bottom metallization pattern, the intermediate metallization pattern, and the bottom metallization pattern, collectively, while allowing electrical communication the first top IC and the second top IC.
Debral teaches a package (150, FIGS. 2A-2C, [0056]) wherein the bottom metallization pattern, the intermediate metallization pattern, and the bottom metallization pattern, collectively, are configured to reduce signal interference between the first top IC and the second top IC, relative to a level of signal interference in the absence of the bottom metallization pattern, the intermediate metallization pattern, and the bottom metallization pattern, collectively, while allowing electrical communication the first top IC and the second top IC (metallic seal structures 122 configured to provide protection against noise problems from separate circuit blocks [0004], openings within seal structures allowing electrical interconnect lines to connect adjacent dies or circuit black areas [0005], and metallic seal structures and metal plane structures configured to potentially control cross-talk while allowing die-to-die routing 130 between adjacent die areas 110, [0066]).
As taught by Debral, one of ordinary skill in the art would utilize and modify the above teaching into Debral to obtain and achieve the package wherein the bottom metallization pattern, the intermediate metallization pattern, and the bottom metallization pattern, collectively, are configured to reduce signal interference between the first top IC and the second top IC, relative to a level of signal interference in the absence of the bottom metallization pattern, the intermediate metallization pattern, and the bottom metallization pattern, collectively, while allowing electrical communication the first top IC and the second top IC as claimed, because metallic seal structures and metallization structures surrounding adjacent die regions while accommodating die-to-die routing reduces cross-talk and noise coupling, and signal interference between adjacent circuit blocks [0004-0005, 0066].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Debral in combination with Debral517 due to above reason.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIYOUNG OH whose telephone number is (703)756-5687. The examiner can normally be reached Monday-Friday, 9AM-5PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached on (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 6/1/26
Prosecution Insights