DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) submitted on November 10, 2023; December 6, 2024; and August 18, 2025 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Objections
Claim 14 is objected to because of the following informalities: “and” should be inserted before “the second redistribution” (line 3). Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5, 8, 16 and 18-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2023/0387032 A1 (hereinafter “Tong”).
Regarding claim 1, Tong discloses in Fig. 1 and related text a method comprising:
forming a plurality of first conductive elements (112; [0057]) on and extending through a first composite layer (111; [0004] and [0057]);
forming a first polymer layer (122; [0004] and [0058]; note: Ajinomoto build-up film (ABF) is a polymer composite film composed of epoxy resin and silicon dioxide, as evidenced by the attached non-patent literature Materials Today Communications 37 (2023) 107201 in the first line of the Abstract) on the first composite layer;
forming a first metallization pattern (121; [0058] and [0108]) extending through the first polymer layer;
forming a second polymer layer (132; [0060]) over the first polymer layer, wherein the second polymer layer is thinner than the first polymer layer;
forming a second metallization pattern (131; [0060] and [0110]) on and extending through the second polymer layer, wherein the second metallization pattern is thinner than the first metallization pattern;
forming a second composite layer (142; [0061]) on the first composite layer; and
forming a plurality of second conductive elements (141; [0061]) extending through the second composite layer.
Regarding claim 2, Tong discloses forming the first metallization pattern comprises:
patterning the first polymer layer using a lithography mask to expose a first conductive element (112 (upper horizontal portion thereof); Figs. 1, 11E; [0057] and [0108]); and
depositing a conductive material (copper (Cu)) on the first polymer layer and on the exposed first conductive element (Fig. 11E; [0108]).
Regarding claim 5, Tong shows the first polymer layer physically contacts the first composite layer (Fig. 1).
Regarding claim 8, Tong discloses the first polymer layer and the second polymer layer comprise different polymers ([0058] and [0060]).
Regarding claim 16, Tong discloses in Fig. 1 and related text a package (100; [0056]) comprising:
a first composite layer (142; [0061]);
a second composite layer (111; [0057]) on the first composite layer;
a plurality of conductive elements (112, 141; [0057] and [0061]) within the first composite layer and the second composite layer;
a first redistribution structure (120; [0058]) on the second composite layer, wherein the first redistribution structure comprises a plurality of first polymer layers (122; [0058]) and a plurality of first conductive lines (121; [0058] and [0062]);
a second redistribution structure (130; [0059]) on the first redistribution structure, wherein the second redistribution structure comprises a plurality of second polymer layers (132; [0060]) and a plurality of second conductive lines (131; [0060] and [0062]), wherein the second polymer layers are thinner than the first polymer layers, wherein the second conductive lines are thinner than the first conductive lines; and
a semiconductor device (570; [0084]) attached to the second redistribution structure.
Regarding claim 18, Tong shows the first composite layer, the second composite layer, the first redistribution structure, and the second redistribution structure have coplanar sidewalls (Fig. 1).
Regarding claim 19, Tong shows a thickness of the first redistribution structure is greater than a thickness of the second redistribution structure (Fig. 1).
Regarding claim 20, Tong shows a combined thickness of the first composite layer and the second composite layer is greater than a thickness of the second redistribution structure (Fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 4, 6, 7, 9, 10, 13 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tong.
Regarding claim 3, Tong discloses, in the embodiment of Fig. 1, the method of claim 1.
Tong does not disclose, in the embodiment of Fig. 1, connecting a plurality of integrated circuit dies to the second metallization pattern.
Tong teaches, in the embodiment of Fig. 8, connecting a plurality of integrated circuit dies (32, 33; [0097]) to the second metallization pattern.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to connect a plurality of integrated circuit dies to the second metallization pattern, as taught by Tong in the embodiment of Fig. 8, in order to provide a processor and a High Bandwidth Memory (HBM) for high-performance computing, data center, and/or artificial intelligence (AI) applications (Tong: [0097]).
Regarding claim 4, Tong discloses, in the embodiment of Fig. 1, the method of claim 1.
Tong does not disclose, in the embodiment of Fig. 1, the first composite layer comprises a layer of prepreg material.
Tong teaches, in the embodiment of Fig. 2, the first composite layer (211B; [0066]) comprises a layer of prepreg material.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the first composite layer to comprise a layer of prepreg material, as taught by Tong in the embodiment of Fig. 2, in order to enable an electronic component to be disposed in a pre-punched opening formed in the first composite layer (Tong: [0066]).
Regarding claim 6, Tong discloses, in the embodiment of Fig. 1, the method of claim 1.
Tong does not disclose, in the embodiment of Fig. 1, before forming the second composite layer, forming a plurality of third conductive elements on the first composite layer and on the plurality of first conductive elements.
Tong teaches, in the embodiment of Figs. 12C-12D, before forming the second composite layer, forming a plurality of third conductive elements (311; [0117]) on the first composite layer (412B; [0117]) and on the plurality of first conductive elements (313; [0118]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, before forming the second composite layer, to form a plurality of third conductive elements on the first composite layer and on the plurality of first conductive elements, as taught by Tong in the embodiment of Figs. 12C-12D, in order to use the third conductive elements to conduct heat to the outside, thereby improving the thermal management of the package (Tong: [0081]).
Regarding claim 7, Tong discloses, in the embodiments of Figs. 1 and 12C-12D, the method of claim 6.
Tong does not disclose, in the embodiment of Fig. 1, a thickness of the plurality of third conductive elements is greater than a thickness of the first metallization pattern.
Tong teaches, in the embodiment of Figs. 4 and 12E, a thickness of the plurality of third conductive elements (311; [0081] and [0117]) is greater than a thickness of the first metallization pattern (121; [0058] and [0062]; note: reference numeral 121 is included in Fig. 1 but is omitted from Figs. 4 and 12E).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a thickness of the plurality of third conductive elements to be greater than a thickness of the first metallization pattern, as taught by Tong in the embodiment of Figs. 4 and 12E, in order to tailor the thermal properties of the material (e.g., Cu-Invar-Cu or Cu-Mo-Cu) of which the third conductive elements are made, thereby improving the thermal management of the package (Tong: [0081]).
Regarding claim 9, Tong discloses in Figs. 11D-11G and related text a method comprising:
forming a first interconnect layer (210; Fig. 11F; [0107]) on a first carrier substrate (C1; Fig. 11F; [0109]), wherein the first interconnect layer comprises a first composite material (211B (e.g., BT/glass fabric); Fig. 11D; [0066] and [0106]);
forming a first redistribution structure (120; Fig. 11E; [0108]) on the first interconnect layer, wherein forming the first redistribution structure comprises:
depositing a first dielectric layer ([0108]);
patterning the first dielectric layer using a lithography mask ([0108]); and
depositing a first conductive material on the first dielectric layer ([0108]);
forming a second redistribution structure (130; Fig. 11G; [0110]) on the first redistribution structure, wherein forming the second redistribution structure comprises:
depositing a second dielectric layer ([0110]);
patterning the second dielectric layer using a lithography mask (implied by “patterning” and “photoresist removal” in [0110]); and
depositing a second conductive material on the second dielectric layer ([0110]).
Tong does not disclose, in the embodiment of Figs. 11D-11G, attaching an integrated circuit die to the second redistribution structure.
Tong teaches, in the embodiment of Fig. 5, attaching an integrated circuit die (570; [0084]) to the second redistribution structure.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to attach an integrated circuit die to the second redistribution structure, as taught by Tong in the embodiment of Fig. 5, in order to equip the package with a processor, memory, etc. for high-performance computing, data center, and/or artificial intelligence (AI) applications (Tong: [0003]).
Regarding claim 10, Tong shows the first conductive material is deposited to a first thickness and the second conductive material is deposited to a second thickness that is less than the first thickness (Fig. 11G).
Regarding claim 13, Tong discloses forming a second interconnect layer (140; Fig. 11E; [0108]) on the first interconnect layer, wherein the second interconnect layer comprises a second composite material (142; [0061]; note: reference numeral 142 is included in Fig. 1 but is omitted from Fig. 11E), wherein the second interconnect layer is electrically connected to the first interconnect layer (Fig. 11E).
Regarding claim 17, Tong discloses, in the embodiment of Fig. 1, the package of claim 16.
Tong does not disclose, in the embodiment of Fig. 1, an encapsulant over the semiconductor device, wherein the encapsulant and the second redistribution structure have coplanar sidewalls.
Tong teaches, in the embodiment of Fig. 9, an encapsulant (41; [0098]) over the semiconductor device (42, 43; [0098]), wherein the encapsulant and the second redistribution structure (130(13); [0098]) have coplanar sidewalls.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form an encapsulant over the semiconductor device, wherein the encapsulant and the second redistribution structure have coplanar sidewalls, as taught by Tong in the embodiment of Fig. 9, in order to protect the semiconductor device from environmental contaminants.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tong in view of US 2024/0145398 A1 (hereinafter “Hsu”).
Regarding claim 11, Tong discloses the method of claim 9.
Tong does not disclose the first dielectric layer comprises at least one of polybenzoxazole (PBO), polyimide, or benzocyclobutene (BCB).
Hsu teaches in Fig. 2B and related text the first dielectric layer (20b; [0032]) comprises at least one of polybenzoxazole (PBO), polyimide, or benzocyclobutene (BCB).
Tong and Hsu are analogous art because they both are directed to semiconductor packaging and one of ordinary skill in the art would have had a reasonable expectation of success to modify Tong with the specified features of Hsu because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the first dielectric layer to comprise at least one of polybenzoxazole (PBO), polyimide, or benzocyclobutene (BCB), as taught by Hsu, because polybenzoxazole (PBO) offers significant advantages over Ajinomoto Build-up Film (ABF) in advanced semiconductor packaging, particularly higher thermal stability, superior electrical performance (lower dielectric loss), and photodefinable processing.
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960). MPEP 2144.07.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tong in view of US 2021/0175139 A1 (hereinafter “Fang”).
Regarding claim 12, Tong discloses the method of claim 9.
Tong does not disclose attaching a supporting ring to the second redistribution structure.
Fang teaches in Fig. 2 and related text attaching a supporting ring (40; [0025]) to the second redistribution structure (20; [0020]).
Tong and Fang are analogous art because they both are directed to semiconductor packaging and one of ordinary skill in the art would have had a reasonable expectation of success to modify Tong with the specified features of Fang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to attach a supporting ring to the second redistribution structure, as taught by Fang, in order to improve the mechanical strength of the package (Fang: [0026]).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tong in view of US 2019/0295912 A1 (hereinafter “Yu-2019”).
Regarding claim 14, Tong discloses the method of claim 9.
Tong does not disclose performing a sawing process, wherein after performing the sawing process, sidewall surfaces of the first interconnect layer, the first redistribution structure, and the second redistribution structure are coplanar.
Yu-2019 teaches in Fig. 1S and related text performing a sawing process ([0063]), wherein after performing the sawing process, sidewall surfaces of the first interconnect layer (117; [0045]), the first redistribution structure (111; [0031]), and the second redistribution structure (113; [0036]) are coplanar.
Tong and Yu-2019 are analogous art because they both are directed to semiconductor packaging and one of ordinary skill in the art would have had a reasonable expectation of success to modify Tong with the specified features of Yu-2019 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to perform a sawing process, wherein after performing the sawing process, sidewall surfaces of the first interconnect layer, the first redistribution structure, and the second redistribution structure are coplanar, as taught by Yu-2019, because of the vertical path of the saw blade (143) (Yu-2019: [0063]).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tong in view of US 2020/0006089 A1 (hereinafter “Yu-2020”).
Regarding claim 15, Tong discloses the method of claim 9.
Tong does not disclose before forming the first interconnect layer, depositing a seed layer on the first carrier substrate.
Yu-2020 teaches in Fig. 5 and related text before forming the first interconnect layer, depositing a seed layer (44; [0027]) on the first carrier substrate (20; [0026]).
Tong and Yu-2020 are analogous art because they both are directed to semiconductor packaging and one of ordinary skill in the art would have had a reasonable expectation of success to modify Tong with the specified features of Yu-2020 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, before forming the first interconnect layer, to deposit a seed layer on the first carrier substrate, as taught by Yu-2020, in order to facilitate the copper (Cu) plating process referred to in [0107] of Tong.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M ALBRECHT whose telephone number is (571)272-7813. The examiner can normally be reached M-F 9:30 AM - 6:30 PM (CT).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PETER M ALBRECHT/Primary Examiner, Art Unit 2811
Prosecution Insights