DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species 2 in the reply filed on May 12 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claims 1-6, 9-13, and 15-23 are examined. The Restriction/Election Requirement is made final.
Claim Objections
Claims 9-10 and 15 are objected to because of the following informalities.
Regarding claim 9: “further comprising:
additional first word line extending in the first direction; and
additional first word line column coupled to the additional first word line through additional first conductive via…” is grammatically incorrect.
Regarding claim 10: “further comprising:
additional second word line extending in the first direction; and
additional second word line column coupled to the additional second word line through additional second conductive via…” is grammatically incorrect.
Regarding claim 15, “further comprising:
additional first word line disposed parallel to the first word line;
additional second word line disposed parallel to the second word line, the additional first word line overlapping the additional second word line in the top-down view;
additional second word line column disposed between the additional first and second word lines, the additional second word line column being disposed on the first side of the first bit line; and
additional second conductive via connected to the additional second word line column and the additional second word line” is grammatically incorrect.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 9-13, and 15-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Vereen et al. (“Vereen” US 2013/0210211).
Regarding claim 1, Vereen discloses a device (Figure 15), comprising:
a first word line (1502, lower) and a second word line (1502, upper) disposed over the first word line (1502, lower), the first and second word lines (1502 lower and upper) extending in a first direction (Y-direction labeled in Figure 15);
a first bit line (104, lower) between the first and second word lines (1502 lower and upper) and extending a second direction (X-direction labeled in Figure 15);
a first word line column (1508) disposed on a first side of the first bit line (104, lower, see Figure 15) and extending in a third direction (Z-direction labeled in Figure 15), the first word line column (1505) being coupled to the first word line (1502, lower) through a first conductive via (1510), wherein the first, second, and third directions are different (X, Y, and Z directions are orthogonal to each other);
a second word line column (1505) extending in the third direction (Z-direction) and disposed on a second side of the first bit line (104, lower) opposite to the first side (see Figure 15), the second word line column (1505) being coupled to the second word line (1502, upper) through a second conductive via (1510, see Figure 15), wherein the first and second conductive vias (1510) are offset in the first and third direction (Y and Z directions, see Figure 15);
a selector layer (608, outer IMO layer, para. [0045], which can comprise memory cell 106 shown in Figure 15) lining the first and second sides of the first bit line (104, see Figure 6); and
a memory layer (604) lining the selector layer (608) and connected to the first and second word line columns (see Figure 6).
The Examiner has considered the insulating metal oxide layer (IMO, 608) as the claimed selector layer because the function of the IMO layer is similar to that of, for example, an ovonic threshold switching (OTS) selector layer. The IMO layer uses trap assisted tunneling to access or “select” the memory layer, thus is considered as a selector layer.
Regarding claim 2, Vereen further discloses a second bit line (104, upper) disposed over the first bit line (104, lower) in the third direction (Z-direction, see Figure 15) and interposed between the first and second word line columns (1508, 1505) in the first direction (Y-direction, see Figure 15), and the selector layer (608) lining the second bit line (104, see Figures 15 and 6).
Regarding claim 3, Vereen discloses wherein the first and second conductive vias (1510) are offset in the second direction (X-direction, see Figure 15).
Regarding claim 4, Vereen discloses wherein the first word line column (1508) is separated from the second word line (1502, upper) in the third direction (Z-direction) by a dielectric layer, and the second conductive via (1510) is laterally covered by the dielectric layer (see Figure 20, the dielectric layer is not explicitly labeled, but is clearly a dielectric layer or else would cause electric shortages).
Regarding claim 5, Vereen discloses wherein the second word line column (1505) is separated from the first word line (1502, lower) in the third direction (Z-direction) by a dielectric layer, and the first conductive via (1510) is laterally covered by the dielectric layer (see Figure 20, the dielectric layer is not explicitly labeled, but is clearly a dielectric layer or else would cause electric shortages.
Regarding claim 6, Vereen discloses a first memory cell (106, see Figure 16A) comprising a portion of the first bit line (104, lower), a portion of the first word line column (1508) connected to the first word line (1502, lower) through the first conductive via (1510), a portion of the selector layer (608, part of memory cell 106, see Figure 6), and a portion of the memory layer (604, see Figure 6); and
a second memory cell (106, see Figure 16A, not labeled, but present) disposed alongside the first memory cell in the first direction (Y-direction in Figure 16A), the second memory cell (106) comprising another portion of the first bit line (104), a portion of the second word line column (1505) connected to the second word line (1502, upper) through the second conductive via (1510), another portion of the selector layer (608, part of memory cell 106, see Figure 6), and another portion of the memory layer (604, see Figure 6).
Regarding claim 9, Vereen discloses additional first word line (1502, lower) extending in the first direction (Y-direction, see Figure 15, see additional first word lines); and
additional first word line column (1508) coupled to the additional first word line (1502, lower) through additional first conductive via (1510), wherein the additional first word line column (1508) is offset from the first word line column (1508) in the first and second directions (see multiple first word line columns offset from each other in the Y and X directions, Figure 15).
Regarding claim 10, Vereen discloses additional second word line (1502, upper) extending in the first direction (Y-direction, see additional second word lines); and
additional second word line column (1505) coupled to the additional second word line (1502, upper) through additional second conductive via (1510), wherein the additional second word line column (1505) is offset from the second word line column (1505) in the first and second directions (see multiple second word line columns offset from each other in the Y and X directions, Figure 15).
Regarding claim 11, Vereen discloses a device (Figure 15), comprising:
a first word line (1502, lower) and a second word line (1502, upper) separated from the first word line, the first word line overlapping the second word line in a top-down view (see Figure 15);
a first bit line (104, lower) between the first and second word lines (1502, lower and upper), the first bit line (104, lower) intersecting the first and second word lines (1502, lower and upper) in the top-down view (see Figure 15);
a first word line column (1508) and a second word line column (1505) disposed on a first side and a second side of the first bit line (104, see Figure 15), respectively, wherein the first and second word line columns (1508, 1505) overlap the first and second word lines (1502, lower and upper) in the top-down view (see Figure 15);
a first conductive via (1510) disposed between and electrically coupled to the first word line (1502, lower) and the first word line column (1508, see Figure 15);
a second conductive via (1510) disposed between and electrically coupled to the second word line (1502, upper) and the second word line column (1505, see Figure 15), the first and second conductive vias (1510) being laterally offset in the top-down view (see Figure 15);
a selector layer (608, outer IMO layer, para. [0045], which can comprise memory cell 106 shown in Figure 15) lining the first and second sides of the first bit line (104, see Figure 6); and
a memory layer (604) lining the selector layer (608) and connected to the first and second word line columns (see Figure 6).
The Examiner has considered the insulating metal oxide layer (IMO, 608) as the claimed selector layer because the function of the IMO layer is similar to that of, for example, an ovonic threshold switching (OTS) selector layer. The IMO layer uses trap assisted tunneling to access or “select” the memory layer, thus is considered as a selector layer.
Regarding claim 12, Vereen discloses a second bit line (104, upper) disposed between the first bit line (104, lower) and the second word line (105, upper), the first and second word line columns (1508, 1505) being disposed at two opposing sides of the second bit line (104, upper, see Figure 15), and the selector layer (608) lining the two opposing sides of the second bit line (104, see Figures 15 and 6).
Regarding claim 13, Vereen discloses wherein bottom surfaces of the selector layer (608) and the first word line column (1508) are substantially level (since the selector layer 608 comprises the outermost surface of the word line column 1508, the bottom surfaces are substantially level in Figure 6, the bottom surfaces being the lower surface of 608 that extends in the Y-direction in Figure 6), the bottom surface of the first word line column (1508) is in contact with the first conductive via (1510, electrically contacting, see Figure 15), and a bottom surface of the memory layer (604, Figure 6 is above the bottom surface of the selector layer 608, the lower surface of 604 is above the lower surface of 608 in the X-direction in Figure 6).
Regarding claim 15, Vereen further discloses additional first word line (1502, lower) disposed parallel to the first word line (1502, see multiple first word lines 1502 parallel to each other);
additional second word line (1502, upper) disposed parallel to the second word line (see Figure 15), the additional first word line overlapping the additional second word line in the top-down view (see Figure 15);
additional second word line column (1505) disposed between the additional first and second word lines (1502, upper and lower, see Figure 15), the additional second word line column being disposed on the first side of the first bit line (104, see Figure 15); and
additional second conductive via (1510) connected to the additional second word line column (1505) and the additional second word line (1502, upper, see Figure 15).
Regarding claim 16, Vereen discloses a method (method of forming device of Figure 15), comprising:
forming a first conductive via (1510) on a first word line (1502, lower);
forming a first bit line (104) over the first conductive via (1510), wherein the first word line (1502) extends in a first direction (Y-direction in Figure 15, see Figure 15), the first bit line (104) extends in a second direction (X-direction in Figure 15) different from the first direction (Y direction and X directions are orthogonal to each other);
forming a selector spacer (608, Figure 6, part of memory cell 106 which is part of the device of Figure 15, see Figure 16A) on two opposing sides of the first bit line (104);
forming a memory spacer (604) on the selector spacer (608, see Figure 6);
forming a first word line column (1508) and a second word line column (1505) in a third direction (Z-direction in Figure 15), wherein the memory spacer (608) lines the first and second word line columns (see Figures 15, 6), the first word line column (1508) lands on the first conductive via (1510), and the third direction (Z-direction) is different from the first and second directions (X, Y, and Z directions are orthogonal to each other);
forming a second conductive via (1510) on the second word line column (1505, see Figure 15); and
forming a second word line (1502, upper) on the second conductive via (1510, see Figure 15).
The Examiner has considered the insulating metal oxide layer (IMO, 608) as the claimed selector spacer because the function of the IMO layer is similar to that of, for example, an ovonic threshold switching (OTS) selector. The IMO layer uses trap assisted tunneling to access or “select” the memory layer, thus is considered as a selector spacer.
Regarding claim 17, Vereen discloses forming a dielectric layer (shown in Figure 20) on the first word line (1502, lower); and
forming the first conductive via (1510) in the dielectric layer (see Figure 20), wherein after forming the second word line column (1505), the second word line column (1505) is isolated from the first word line (1502, lower) through the dielectric layer (see Figures 15 and 20, it is clear the layers in which the conductive lines are embedded, see Figure 20, are dielectric layers or else there would be electrical shortages).
Regarding claim 18, Vereen further discloses forming a dielectric layer (see Figure 20) on the first and second word line column (1508, 1505); and
forming the second conductive via (1510) in the dielectric layer (see Figure 20), wherein after forming the second word line (1502, upper), the first word line column (1508) is isolated from the second word line (1502, upper) through the dielectric layer (see Figures 15, 20).
Regarding claim 19, Vereen further discloses forming a dielectric layer (see Figure 20, and 12A-12H) on the first bit line (104) before forming the first and second word line columns (see Figures 12A-12H); and
forming a second bit line (104, upper) on the dielectric layer, wherein the second bit line overlaps the first bit line in a top-down view (see Figure 15, 20).
Regarding claim 20, Vereen discloses wherein forming the first and second conductive vias (1510) comprise:
forming the first and second conductive vias (1510) in a checkerboard pattern matrix in a plan view (see Figures 15, 16A).
Regarding claim 21, Vereen discloses wherein the memory layer (604) is disposed between the selector layer (608) and the first word line column (analogous to 602 in Figure 6) in the second direction (Y-direction, see Figure 6), and the selector layer and the memory layer are interfaced with a sidewall of the first word line column (see Figures 6, 15).
Regarding claim 22, Vereen discloses wherein the memory layer (604) surrounds the first word line column (analogous to 602 in Figure 6) in the first direction and the second direction (Y and X directions), and the selector layer (608) surrounds the memory layer (604) in the first direction and the second direction (see Figure 6).
Regarding claim 23, Vereen discloses wherein the first bit line and the second bit line (104, upper and lower) overlap and are substantially aligned with each other in the third direction (Z-direction, see Figure 15).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights