Prosecution Insights
Last updated: July 17, 2026
Application No. 18/507,114

PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF

Non-Final OA §103
Filed
Nov 13, 2023
Examiner
GARCES, NELSON Y
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Vanguard International Semiconductor Corporation
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
83%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
471 granted / 587 resolved
+12.2% vs TC avg
Minimal +3% lift
Without
With
+2.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
28 currently pending
Career history
631
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
76.6%
+36.6% vs TC avg
§102
15.9%
-24.1% vs TC avg
§112
5.6%
-34.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 587 resolved cases

Office Action

§103
DETAILED ACTION This action is responsive to the application No. 18/507,114 filed on November 13, 2023. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species 1 reading on Fig. 1 in the reply filed on 04/29/2026 is acknowledged. The Applicants indicated that claims 1-20 read on the elected species. Accordingly, pending in this Office action are claims 1-20. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 2, 5, 8, 10-12, 16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Danno (US 2017/0301643) in view of Kelaiti (US 2026/0114289). Regarding Claim 1, Danno (see, e.g., Figs. 12, 22, 26), teaches a package structure, comprising: a lead frame LF, comprising a cavity (i.e., cavity accommodating semiconductor chip CP1) (see, e.g., par. 0099); a die CP1, disposed in the cavity, wherein the die CP1 comprises: a substrate, having a first surface (i.e., top surface) and a second surface (i.e., bottom surface); a bonding pad P1, disposed on the first surface (see, e.g., par. 0053); and a backside metal layer BE, disposed on the second surface (see, e.g., par. 0074); a bonding wire BW, electrically connecting the bonding pad P1 to the lead frame LF (see, e.g., par. 0051); a first bonding material BD1, disposed between the backside metal layer BE and the cavity, wherein the die CP1 is soldered onto the lead frame LF through the first bonding material BD1 (see, e.g., par. 0074); and a molding material MR, encapsulating the die CP1 and the bonding wire BW, and covering the lead frame LF (see, e.g., par. 0051). Danno is silent with respect to the claim limitation that the bonding material is solder. Danno discloses the claimed invention except for the use of silver paste or a thermosetting bonding material instead of solder. Kelaiti (see, e.g., Fig. 8, par. 0083), on the other hand teaches that solder and silver paste are equivalent materials known in the art. Therefore, because these conductive materials were art-recognized equivalents at the time of the invention, one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, one of ordinary skill in the art would have found it obvious to substitute solder for silver paste since the substitution would yield predictable results. See Supreme Court decision in KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 YSPQ2d 1385 (2007). Regarding Claim 2, Danno and Kelaiti teach all aspects of claim 1. Danno (see, e.g., Figs. 12, 22, 26), teaches: a printed circuit board PB1, disposed below the lead frame LF (see, e.g., par. 0230); and a second solder BD3, disposed between the lead frame LF and the printed circuit board PB1, wherein the lead frame LF is soldered onto the printed circuit board PB1 through the second solder BD3 (see, e.g., par. 0240). Regarding Claim 5, Danno and Kelaiti teach all aspects of claim 1. Danno (see, e.g., Figs. 12, 22, 26), teaches that the substrate comprises a core layer and a composite material layer wrapping around the core layer, or a semiconductor substrate (see, e.g., par. 0051). Regarding Claim 8, Danno and Kelaiti teach all aspects of claim 1. Danno (see, e.g., Figs. 12, 22, 26), teaches that the backside metal layer BE comprises a single-layered structure or a multi-layered structure, the composition of the single-layered structure comprises Au, Ag, Cu or a pre-solder material, and the composition of the multi-layered structure is selected from a group consisting of Ti/Ni/Ag, Ti/NiV/Ag, Ti/Ni/Au, Ti/Cu, Ti/Au, Cu/Ni/Au, Ni/Pd/Au, Ni/Au, Au/As, Al/Ni/Ag and a combination thereof (see, e.g., par. 0146). Regarding Claim 10, Danno and Kelaiti teach all aspects of claim 1. Danno (see, e.g., Figs. 12, 22, 26), teaches that a depth of the cavity is one-quarter to one-half of a thickness of the lead frame (see, e.g., Fig. 22). Regarding Claim 11, Danno (see, e.g., Figs. 12, 22, 26), teaches a method of fabricating a package structure, comprising: providing a lead frame LF and forming a cavity (i.e., cavity accommodating semiconductor chip CP1) in the lead frame LF (see, e.g., par. 0099); providing a die CP1, comprising: providing a substrate having a first surface (i.e., top surface) and a second surface (i.e., bottom surface); forming a bonding pad P1 on the first surface (see, e.g., par. 0053); and forming a backside metal layer BE on the second surface (see, e.g., par. 0074); disposing the die CP1 in the cavity; using a first bonding material BD1 to solder the backside metal layer BE of the die CP1 onto the lead frame LF (see, e.g., par. 0074); forming a bonding wire BW to electrically connect the bonding pad P1 to the lead frame LF (see, e.g., par. 0051); and using a molding material MR to encapsulate the die CP1 and the bonding wire BW, and cover the lead frame LF (see, e.g., par. 0051). Danno is silent with respect to the claim limitation that the bonding material is solder. Danno discloses the claimed invention except for the use of silver paste or a thermosetting bonding material instead of solder. Kelaiti (see, e.g., Fig. 8, par. 0083), on the other hand teaches that solder and silver paste are equivalent materials known in the art. Therefore, because these conductive materials were art-recognized equivalents at the time of the invention, one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, one of ordinary skill in the art would have found it obvious to substitute solder for silver paste since the substitution would yield predictable results. See Supreme Court decision in KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 YSPQ2d 1385 (2007). Regarding Claim 12, Danno and Kelaiti teach all aspects of claim 11. Danno (see, e.g., Figs. 12, 22, 26), teaches: providing a printed circuit board PB1 to be disposed below the lead frame LF (see, e.g., par. 0230); and using a second solder BD3 to solder the lead frame LF onto the printed circuit board PB1 (see, e.g., par. 0240). Regarding Claim 16, Danno and Kelaiti teach all aspects of claim 11. Danno (see, e.g., Figs. 12, 22, 26), teaches that providing the substrate comprises providing a semiconductor substrate, or providing a core layer and forming a composite material layer to wrap around the core layer (see, e.g., par. 0051). Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Danno (US 2017/0301643) in view of Kelaiti (US 2026/0114289) and further in view of Feng (US 2011/0018116). Regarding Claim 18, Danno and Kelaiti teach all aspects of claim 11. Danno (see, e.g., Figs. 12, 22, 26), teaches that the backside metal layer BE comprises a single-layered structure or a multi-layered structure, the composition of the single-layered structure comprises Au, Ag, Cu or a pre-solder material, and the composition of the multi-layered structure is selected from a group consisting of Ti/Ni/Ag, Ti/NiV/Ag, Ti/Ni/Au, Ti/Cu, Ti/Au, Cu/Ni/Au, Ni/Pd/Au, Ni/Au, Au/As, Al/Ni/Ag and a combination thereof (see, e.g., par. 0146). Danno is silent with respect to the claim limitation that forming the backside metal layer comprises evaporation, sputtering or plating process. Feng (see, e.g., Fig. 2K), on the other hand, teaches using evaporation, sputtering or electroplating to form a back conductive layer 104 equivalent to the BE of Danno (see, e.g., par. 0022). Danno discloses the claimed invention except for not specifying the material method of formation of the backside metal layer BE. Feng, on the other hand, teaches that using evaporation, sputtering or plating processes in equivalent structures is well known in the art. Therefore, because evaporation, sputtering or plating, were well-known deposition processes used in the formation of metal electrodes at the time of the invention, one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, one of ordinary skill in the art would have found it obvious to use evaporation, sputtering or plating for the formation of the backside metal layer in Danno’s device since the substitution would yield predictable results. See Supreme Court decision in KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 YSPQ2d 1385 (2007). Allowable Subject Matter Claims 3, 4, 6, 7, 9, 13-15, 17, 19, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garces whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Nelson Garces/Primary Examiner, Art Unit 2814
Read full office action

Prosecution Timeline

Nov 13, 2023
Application Filed
Jun 04, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
83%
With Interview (+2.7%)
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 587 resolved cases by this examiner. Grant probability derived from career allowance rate.

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