DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Shuai (U.S. PGPub 2022/0209017) in view of Choi (U.S. PGPub 2014/0056071).
Regarding claim 1, Shuai teaches a flash memory structure ([0001]) comprising:
a semiconductor substrate with an active area and shallow trench isolations (Fig. 1, AA, STI, [0031]), wherein said active area comprises a source line doped region extending in a first direction and multiple branch doped regions extending in a second direction at two sides of said source line doped region, and said branch doped regions are isolated by said shallow trench isolations (SL extending in Y direction [0031], Fig. 2; Fig. 1, AA extending in X direction; [0039], AA formed in substrate 100 which is P-doped),
an erase gate on said source line doped region and extending in said first direction (Fig. 1, EG, extending in Y direction, [0034]) and
multiple memory cells, each said memory cell is provided with a floating gate on one said branch doped region at one side of said erase gate (FG, Figs. 1-2, [0032]).
Shuai does not explicitly teach wherein the multiple branch doped regions are alternately arranged along said first direction.
Choi teaches a memory device comprising a semiconductor substrate with an active area and shallow trench isolations, wherein the active area comprises a line region extending in a first direction and multiple branch doped regions extending in a second direction at two sides of said line region, and said branch doped regions are isolated by said shallow trench isolations (Figs. 2A-2C, branch regions A, STI regions F; line region corresponds to common source line in Fig. 2A, [0027]-[0029]), and multiple memory cells, each memory cell provided with a floating gate on one said branch doped region (Fig. 2C, 22, [0030]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Choi with Shuai such that the multiple branch doped regions are alternately arranged along said first direction for the purpose of reducing resistance and capacitance of the lines (Choi, [0033]).
Regarding claim 2, the combination of Shuai and Choi teaches wherein said branch doped region at one side of said source line doped region corresponds to one said shallow trench isolation at the other side of said source line doped region (Shuai, Fig. 1; Choi, Fig. 2B). It would have been obvious to a person having ordinary skill in the art before the time of the effective filing date for the reasons set forth in the rejection of claim 1.
Claims 3-6 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Shuai (U.S. PGPub 2022/0209017) in view of Choi (U.S. PGPub 2014/0056071) and Huang (U.S. PGPub 2021/0183875).
Regarding claim 3, the combination of Shuai and Choi teaches wherein multiple said branch doped regions constitutes a bit cell block (Shuai, [0002]; Choi, [0037]) but does not explicitly teach wherein an erase gate strap is in the middle of said bit cell block.
Huang teaches wherein an erase gate strap is in a bit cell block and wherein the strap cell is laid out at a spacing to minimize voltage drops ([0021]-[0022], erase gate strap cell).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Huang with Shuai and Choi such that wherein an erase gate strap is in the middle of said bit cell block for the purpose of coupling strap lines to metallization layers at an appropriate density (Huang, [0021]-[0022]).
Regarding claim 4, the combination of Shuai, Choi, and Huang teaches wherein two control gates respectively on said floating gates at two sides of said source line doped region and extending in said first direction through multiple said branch doped regions (Shuai, Figs. 1-2, CG, [0034]) and one end of said bit cell block is further provided with a control gate strap ([0024]-[0025], CGWL). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Shuai, Choi, and Huang for the same reasons in the rejection of claim 3.
Regarding claim 5, the combination of Shuai, Choi, and Huang teaches wherein said control gate is provided with a protruding part extending in said second direction on said control gate strap, and said control gate is connected to a first metal layer through a control gate contact on said protruding part (Huang, Fig. 6A, 602, 122, [0061]-[0062]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Shuai, Choi, and Huang for the same reasons in the rejection of claim 3.
Regarding claim 6, the combination of Shuai, Choi, and Huang teaches two word lines respectively at outer sides of said floating gates and extending in said first direction through multiple said branch doped regions (Shuai, Figs. 1-2, WL, [0032]) and one end of said bit cell block is further provided with a word line strap (Huang, word-line strap cells, [0024]-[0025]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Shuai, Choi, and Huang for the same reasons in the rejection of claim 3.
Regarding claim 8, the combination of Shuai, Choi, and Huang teaches wherein said word line is connected to a first metal layer through a word line contact on said word line strap (Figs. 8-9, [0066]-[0068], 108). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Shuai, Choi, and Huang for the same reasons in the rejection of claim 3.
Regarding claim 9, the combination of Shuai, Choi, and Huang teaches wherein said erase gate is connected to a first metal layer through an erase gate contact on said erase gate strap ([0048]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Shuai, Choi, and Huang for the same reasons in the rejection of claim 3.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Shuai (U.S. PGPub 2022/0209017) in view of Choi (U.S. PGPub 2014/0056071), Huang (U.S. PGPub 2021/0183875), and Chu (U.S. PGPub 2010/0008141).
Regarding claim 7, the combination of Shuai, Choi, and Huang does not explicitly teach wherein said source line doped region is connected to a first metal layer through a source line contact on said word line strap.
Chu teaches wherein strap cells may be WL/CS strap-contact cells ([0030]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Chu with Shuai, Choi, and Huang such that said source line doped region is connected to a first metal layer through a source line contact on said word line strap for the purpose of optimizing signal transmission and minimizing area (Chu, [0030]).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Shuai (U.S. PGPub 2022/0209017) in view of Choi (U.S. PGPub 2014/0056071) and Tran (U.S. PGPub 2019/0164984).
Regarding claim 10, the combination of Shuai and Choi teaches a first metal layer on said semiconductor substrate, said first metal layer comprises multiple metal line patterns (Choi, BL, Fig. 2A, 2C, [0031]),
but does not explicitly teach wherein each said metal line pattern is provided with a bending part right above said source line doped region and two straight parts respectively at two ends of said bending part and right above two of said branch doped regions at two sides of said source line doped region and extending in said second direction.
Tran teaches a semiconductor substrate with an erase gate extending in a first direction ([0044], 16), multiple branch doped regions extending in a second direction at two sides of the erase gate, the multiple branch doped regions isolated by shallow trench isolations (Fig. 11, 36/34, [0044]), and multiple memory cells, each memory cell provided with a floating gate on one branch doped region at one side of said erase gate (Figs. 1-2, [0035]),
and a first metal layer comprising multiple metal line patterns, wherein each metal line pattern is provided with a bending part right above the erase gate and two straight parts respectively at two ends of said bending part and right above two of said branch doped regions at two sides of said erase gate and extending in said second direction (Fig. 11, BL0/1/2, [0044]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Tran with Shuai, Choi, and Tran such that each said metal line pattern is provided with a bending part right above said source line doped region and two straight parts respectively at two ends of said bending part and right above two of said branch doped regions at two sides of said source line doped region and extending in said second direction for the purpose of independently operating the drain regions for each memory cell pair (Tran, [0044]).
Regarding claim 11, the combination of Shuai, Choi, and Tran teaches wherein two said straight parts of each said metal line pattern are connected respectively with two said branch doped regions through bit line contacts (Tran, Fig. 11, 20, [0044]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Shuai, Choi, and Tran for the same reasons in the rejection of claim 11.
Claims 12 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Shuai (U.S. PGPub 2022/0209017) in view of Tran (U.S. PGPub 2019/0164984).
Regarding claim 12, Shuai teaches a flash memory structure ([0001]) comprising:
a semiconductor substrate with an active area and shallow trench isolations (Fig. 1, AA, STI, [0031]), wherein said active area comprises a source line doped region extending in a first direction and multiple branch doped regions extending in a second direction at two sides of said source line doped region, and said branch doped regions are isolated by said shallow trench isolations (SL extending in Y direction [0031], Fig. 2; Fig. 1, AA extending in X direction; [0039], AA formed in substrate 100 which is P-doped),
an erase gate on said source line doped region and extending in said first direction (Fig. 1, EG, extending in Y direction, [0034]) and
multiple memory cells, each said memory cell is provided with a floating gate on one said branch doped region at one side of said erase gate (FG, Figs. 1-2, [0032]).
Shuai does not explicitly teach a first metal layer on said semiconductor substrate, said first metal layer comprises multiple metal line patterns, wherein each said metal line pattern is provided with a bending part right above said source line doped region and two straight parts respectively at two ends of said bending part right above two of said branch doped regions at two sides of said source line doped region and extending in said second direction.
Tran teaches a semiconductor substrate with an erase gate extending in a first direction ([0044], 16), multiple branch doped regions extending in a second direction at two sides of the erase gate, the multiple branch doped regions isolated by shallow trench isolations (Fig. 11, 36/34, [0044]), and multiple memory cells, each memory cell provided with a floating gate on one branch doped region at one side of said erase gate (Figs. 1-2, [0035]),
and a first metal layer comprising multiple metal line patterns, wherein each metal line pattern is provided with a bending part right above the erase gate and two straight parts respectively at two ends of said bending part and right above two of said branch doped regions at two sides of said erase gate and extending in said second direction (Fig. 11, BL0/1/2, [0044]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Tran with Shuai, Choi, and Tran such that each said metal line pattern is provided with a bending part right above said source line doped region and two straight parts respectively at two ends of said bending part and right above two of said branch doped regions at two sides of said source line doped region and extending in said second direction for the purpose of independently operating the drain regions for each memory cell pair (Tran, [0044]).
Regarding claim 21, the combination of Shuai and Tran teaches wherein two said straight parts of each said metal line pattern are connected respectively with two said branch doped regions through bit line contacts (Tran, Fig. 11, 20, [0044]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Shuai, Choi, and Tran for the same reasons in the rejection of claim 11.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Shuai (U.S. PGPub 2022/0209017) in view of Tran (U.S. PGPub 2019/0164984) and Choi (U.S. PGPub 2014/0056071).
Regarding claim 13, the combination of Shuai and Tran does not explicitly teach wherein the multiple branch doped regions are alternately arranged along said first direction.
Choi teaches a memory device comprising a semiconductor substrate with an active area and shallow trench isolations, wherein the active area comprises a line region extending in a first direction and multiple branch doped regions extending in a second direction at two sides of said line region, and said branch doped regions are isolated by said shallow trench isolations (Figs. 2A-2C, branch regions A, STI regions F; line region corresponds to common source line in Fig. 2A, [0027]-[0029]), and multiple memory cells, each memory cell provided with a floating gate on one said branch doped region (Fig. 2C, 22, [0030]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Choi with Shuai and Tran such that the multiple branch doped regions are alternately arranged along said first direction for the purpose of reducing resistance and capacitance of the lines (Choi, [0033]).
Claims 14-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shuai (U.S. PGPub 2022/0209017) in view of Tran (U.S. PGPub 2019/0164984) and Huang (U.S. PGPub 2021/0183875)
Regarding claim 14, the combination of Shuai and Tran teaches wherein multiple said branch doped regions constitutes a bit cell block (Shuai, [0002]) but does not explicitly teach wherein an erase gate strap is in the middle of said bit cell block.
Huang teaches wherein an erase gate strap is in a bit cell block and wherein the strap cell is laid out at a spacing to minimize voltage drops ([0021]-[0022], erase gate strap cell).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Huang with Shuai and Choi such that wherein an erase gate strap is in the middle of said bit cell block for the purpose of coupling strap lines to metallization layers at an appropriate density (Huang, [0021]-[0022]).
Regarding claim 15, the combination of Shuai, Tran, and Huang teaches wherein two control gates respectively on said floating gates at two sides of said source line doped region and extending in said first direction through multiple said branch doped regions (Shuai, Figs. 1-2, CG, [0034]) and one end of said bit cell block is further provided with a control gate strap (Huang, [0024]-[0025], CGWL). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Shuai, Tran, and Huang for the same reasons in the rejection of claim 3.
Regarding claim 16, the combination of Shuai, Tran, and Huang teaches wherein said control gate is provided with a protruding part extending in said second direction on said control gate strap, and said control gate is connected to a first metal layer through a control gate contact on said protruding part (Huang, Fig. 6A, 602, 122, [0061]-[0062]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Shuai, Tran, and Huang for the same reasons in the rejection of claim 3.
Regarding claim 17, the combination of Shuai, Tran, and Huang teaches two word lines respectively at outer sides of said floating gates and extending in said first direction through multiple said branch doped regions (Shuai, Figs. 1-2, WL, [0032]) and one end of said bit cell block is further provided with a word line strap (Huang, word-line strap cells, [0024]-[0025]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Shuai, Tran, and Huang for the same reasons in the rejection of claim 3.
Regarding claim 19, the combination of Shuai, Tran, and Huang teaches wherein said word line is connected to a first metal layer through a word line contact on said word line strap (Huang, Figs. 8-9, [0066]-[0068], 108). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Shuai, Tran, and Huang for the same reasons in the rejection of claim 3.
Regarding claim 20, the combination of Shuai, Tran, and Huang teaches wherein said erase gate is connected to a first metal layer through an erase gate contact on said erase gate strap (Huang, [0048]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Shuai, Tran, and Huang for the same reasons in the rejection of claim 3.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Shuai (U.S. PGPub 2022/0209017) in view of Tran (U.S. PGPub 2019/0164984), Huang (U.S. PGPub 2021/0183875), and Chu (U.S. PGPub 2010/0008141).
Regarding claim 18, the combination of Shuai, Tran, and Huang does not explicitly teach wherein said source line doped region is connected to a first metal layer through a source line contact on said word line strap.
Chu teaches wherein strap cells may be WL/CS strap-contact cells ([0030]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Chu with Shuai, Tran, and Huang such that said source line doped region is connected to a first metal layer through a source line contact on said word line strap for the purpose of optimizing signal transmission and minimizing area (Chu, [0030]).
Conclusion
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/ALIA SABUR/ Primary Examiner, Art Unit 2812