Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18507230 filed on 11/13/2023.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Election/Restrictions
Applicant’s election without traverse of claims 8-27 in the reply filed on 5/12/2026 is acknowledged.
Allowable Subject Matter
Claims 8-14 are allowed.
The following is an examiner' s statement of reasons for allowance:
Claims 8-14: The primary reason for the allowance of the claims is the inclusion of the limitation “filling the spaces with a dummy layer; removing a first portion of the dummy layer in the second device region using an etchant while leaving a second portion of the dummy layer in the first device region intact; removing the second portion of the dummy layer; and after removing the second portion of the dummy layer, forming an n-type work function metal layer over the second p-type work function metal layer”, in all of the claims in combination with the remaining features of independent claim 8.
Lee et al. teach a method of forming a semiconductor device, comprising: forming a first fin (Figs. 12A & 12B, element 62) and a second fin (Figs. 12A & 12B, element 62) in a first device region (Figs. 12A & 12B, element 50N) and a second device region (Figs. 12A & 12B, element 50P) on a substrate (Figs. 12A & 12B, element 50), respectively, each of the first fin and the second fin comprises alternately stacked first semiconductor layers (Figs. 12A & 12B, element 64) and second semiconductor layers (Figs. 12A & 12B, element 66); removing the first semiconductor layers to form spaces each between the second semiconductor layers (Figs. 13A & 13B disclose removing elements 64); forming a gate dielectric layer (Figs. 14A & 14B, element 112) wrapping around each of the second semiconductor layers; forming a first p-type work function metal layer (Figs. 18A & 18B, element 114A) wrapping around the second semiconductor layers in the second device region; forming a second p-type work function metal layer (Figs. 20A & 20B, element 114C) on the first p-type work function metal layer.
However, Lee et al. do not teach or render obvious the above-quoted features recited in independent claim 8.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-23, 25-27 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (DE 102023104976 A1).
Regarding Independent claim 15, Lee et al. teach a method of forming a semiconductor device, comprising:
forming a fin (Figs. 12A & 12B, element 62) over a substrate (Figs. 12A & 12B, element 50), the fin comprising alternately stacking first semiconductor layers (Figs. 12A & 12B, element 64) and second semiconductor layers (Figs. 12A & 12B, element 66);
removing the first semiconductor layers to form spaces each between the second semiconductor layers (Figs. 13A & 13B disclose removing elements 64);
forming a gate dielectric layer (Figs. 14A & 14B, element 112) wrapping around each of the second semiconductor layers;
forming a first p-type work function metal layer (Figs. 18A & 18B, elements 114A & 116) between the adjacent second semiconductor layers;
thinning the first p-type work function metal layer (specification discloses “includes thinning the protective layer 116”;
forming a second p-type work function metal layer (Figs. 20A & 20B, element 114C) over the thinned first p-type work function metal layer.
Lee et al. do not explicitly disclose forming an n-type work function metal layer over the second p-type work function metal layer.
However, Lee et al. teach depositing a n-type work function metal layer (Figs. 20A & 20B, element 114D).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to add the n-type work function metal layer on the second p-type work function metal layer with the motivation to reduce power consumption and improve switching speed.
Regarding claim 16, Lee et al. teach wherein the second p-type work function metal layer comprises a multilayer structure (Figs. 20A & 20B, elements 114C & 114E).
Regarding claim 17, Lee et al. teach wherein the second p-type work function metal layer comprises: a main layer (Figs. 20A & 20B, element 114C) over the first p-type work function metal layer; and a cap layer (Figs. 20A & 20B, element 114E) wrapping around the main layer, wherein the cap layer comprises a material different from a material of the main layer (specification discloses main layer comprising “the PWFM is made of titanium nitride” and cap layer comprising “tantalum nitride, titanium carbide, tantalum carbide or the like”).
Regarding claim 18, Lee et al. teach wherein the cap layer is thinner than the first p-type work function metal layer (Figs. 20A & 20B).
Regarding claim 19, Lee et al. teach wherein the main layer is thinner than the first p- type work function metal layer (the specification discloses a range of thickness for the semiconductor layers. Accordingly, the thickness is an art recognized variable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thickness and arrive at the claimed limitation. Furthermore, the applicant has not presented persuasive evidence that the claimed thickness is for a particular purpose that is critical to the overall claimed invention).
Regarding claim 20, Lee et al. teach wherein the second p-type work function metal layer interfaces with the gate dielectric layer (Figs. 20A & 20B).
Regarding Independent claim 21, Lee et al. teach a method of forming a semiconductor device, comprising:
forming nanostructures (Figs. 12A & 12B, elements 66 & 64) extending in a first direction above a substrate (Figs. 12A & 12B, element 50) and spaced apart in a second direction perpendicular to the first direction (Figs. 12 & 12B);
forming a gate dielectric layer (Figs. 14A & 14B, element 112) wrapping around each of the nanostructures;
depositing a first p-type work function metal layer (Figs. 18A & 18B, element 114A) between the adjacent nanostructures;
depositing a second p-type work function metal layer (Figs. 20A & 20B, elements 114C & 114E) in contact with opposite sidewalls of the first p-type work function metal layer and opposite sidewalls of the gate dielectric layer,
wherein the second p-type work function metal layer comprises:
a main layer (Figs. 20A & 20B, element 114C); and
a cap layer (Figs. 20A & 20B, element 114E) over the main layer,
wherein the cap layer has a material different from a material of the main layer (specification discloses main layer comprising “the PWFM is made of titanium nitride” and cap layer comprising “tantalum nitride, titanium carbide, tantalum carbide or the like”).
Lee et al. do not explicitly disclose an n-type work function metal layer covering the second p-type work function metal layer.
However, Lee et al. teach depositing a n-type work function metal layer (Figs. 20A & 20B, element 114D).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to add the n-type work function metal layer on the second p-type work function metal layer with the motivation to reduce power consumption and improve switching speed.
Regarding claim 22, Lee et al. teach wherein the cap layer comprises Si, SiO, TaN, or a combination thereof (specification discloses cap layer comprising “tantalum nitride, titanium carbide, tantalum carbide or the like”).
Regarding claim 23, Lee et al. teach wherein an interface between the first p-type work function metal layer and the second p-type work function metal layer are spaced apart from an interface between the second p-type work function metal layer and the gate dielectric layer by a non-zero lateral distance (Figs. 20A & 20B).
Regarding claim 25, Lee et al. teach wherein the cap layer is absent between the adjacent nanostructures (Figs. 20A & 20B).
Regarding claim 26, Lee et al. teach wherein the first p-type work function metal layer and the second p-type work function metal layer have different thicknesses (Figs. 20A & 20B).
Regarding claim 27, Lee et al. teach wherein the second p-type work function metal layer is thinner than the first p-type work function metal layer layer (the specification discloses a range of thickness for the semiconductor layers. Accordingly, the thickness is an art recognized variable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thickness and arrive at the claimed limitation. Furthermore, the applicant has not presented persuasive evidence that the claimed thickness is for a particular purpose that is critical to the overall claimed invention).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (DE 102023104976 A1) in view of Ching et al. (US 2019/0355827).
Regarding claim 24, Lee et al. teach all of the limitations as discussed above.
Lee et al. do not explicitly disclose wherein a seam is in the first p-type work function metal layer.
Ching et al. teach seams being formed in work function layers due to “conformal or non-conformal deposition process for forming the work function tuning layer” (paragraph 0038).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHAHED AHMED/
Primary Examiner, Art Unit 2813
Prosecution Insights