Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/507,298 filed on April 17, 2026.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Election/Restrictions
5. Applicant’s election without traverse of claims 1-16, Group I, drawn to device, in the reply filed on 04/17/2026 is acknowledged.
6. Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to nonelected method claims, Group II, there being no allowable generic or linking claim.
Specification
7. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Display Device Comprising Pixel Circuit Layer and Growth Substrate and Method for Manufacturing the Same”.
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
10. Claims 1-5, 11, 16 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Kim et al. (US 2022/0352277 A1).
Regarding independent claim 1, Kim et al. teaches a display device comprising (Fig. 14A):
a pixel circuit layer (PCL, para [0254] lower part- see the annotated figure below) including a transistor (T, para [0140], see figure below);
a growth substrate (PSV, para [0140] made of aluminum oxide/AlO.sub.x, para [0155]) disposed on the pixel circuit layer (PCL- lower part);
a light emitting element (11/12/13, para [0114]) disposed on the growth substrate (PSV); and
an electrode (BDE2, para [0255]) disposed on the light emitting element (11/12/13) and electrically connecting the light emitting element (11/12/13) and the transistor (T).
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Regarding claim 2, Kim et al. teaches wherein (Fig. 14A), the growth substrate (PSV) is a base layer for epitaxial growth of the light emitting element (11/12/13, para [0114]) and is a sapphire substrate (PSV, para [0155], made of aluminum oxide/AlO.sub.x which is Sapphire).
Regarding claim 3, Kim et al. teaches wherein (Fig. 14A), the light emitting element (11/12/13, para [0114]) is an inorganic light emitting element, the light emitting element (11/12/13) includes:
a first semiconductor layer (11, para [0114]) disposed on the growth substrate (PSV);
a light emitting layer (12 active layer, para [0114]) disposed on the first semiconductor layer (11);
a second semiconductor layer (13, para [0114]) disposed on the light emitting layer (12);
an electrode layer (BDE1) disposed on the second semiconductor layer (13); and
an insulating layer (CTL) disposed on the electrode layer (BDE1), covering the light emitting layer (12) and the second semiconductor layer (13), and partially exposing the electrode layer (BDE1), and
the electrode (BDE2) electrically connects the electrode layer (BDE1) and the transistor (T).
Regarding claim 4, Kim et al. teaches wherein (Fig. 14A):
sub-pixels (PXL1, PXL2, PXL3) each including the light emitting element (12),
wherein the growth substrate (PSV) is provided in an island shape in each of the sub-pixels (PXL1, PXL2, PXL3).
Regarding claim 5, Kim et al. teaches wherein (Fig. 14A), the growth substrate (PSV) is disposed on an entire area of the pixel circuit layer (PCL- lower part).
Regarding claim 11, Kim et al. teaches wherein (Fig. 14A), at least one of the first semiconductor layer (11), the light emitting layer (12), the second semiconductor layer (13), and the electrode layer (BDE1) includes a curved surface in a cross-sectional view (Fig. 14A).
Regarding claim 16, Kim et al. teaches wherein (Fig. 14A), further comprising:
a color conversion layer (CCL1, para [0258]) disposed on the light emitting element (11/12/13) and converting a wavelength of light emitted from the light emitting element (this is a functional limitation/an intended use).
Allowable Subject Matter
11. Claims 6 (claims 7-10 depend on the claim 6), 12 (claim 13 depends on the claim 12), 14 (claim 15 depends on the claim 14) are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
12. Claim 6: the prior art of record alone or in combination neither teaches nor makes obvious the display device comprising:
Claim 6 recites …. the first semiconductor layer, the light emitting layer, the second semiconductor layer, and the electrode layer are sequentially stacked on an upper surface of the growth substrate in a direction inclined with respect to the upper surface of the growth substrate, and
lower surfaces of the first semiconductor layer, the light emitting layer, the second semiconductor layer, and the electrode layer are positioned on a same plane.
Claim 12 recites …. the light emitting layer and the second semiconductor layer are spaced apart from the growth substrate, and
a portion of the electrode layer contacts the growth substrate.
Claim 14 recites …. the first semiconductor layer has an inclined surface inclined with respect to an upper surface of the growth substrate, and
each of the light emitting layer, the second semiconductor layer, and the electrode layer has a substantially constant thickness in a direction perpendicular to the inclined surface and is stacked on the inclined surface.
The prior art, Kim et al. (US 2022/0352277 A1) does not disclose the lower surfaces of the light-emitting element comprising the first semiconductor layer, the light emitting layer, the second semiconductor layer, and the electrode layer are positioned on a same plane, therefore, either by itself or in combination with other arts fail to disclose the above quoted limitations in the section 12.
Examiner’s Note
13. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
15. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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