Prosecution Insights
Last updated: May 29, 2026
Application No. 18/507,817

POST PASSIVATION INTERCONNECT

Non-Final OA §102
Filed
Nov 13, 2023
Priority
Nov 29, 2016 — provisional 62/427,786 +3 more
Examiner
ASSOUMAN, HERVE-LOUIS Y
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
607 granted / 666 resolved
+23.1% vs TC avg
Minimal +4% lift
Without
With
+4.2%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
25 currently pending
Career history
697
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
83.1%
+43.1% vs TC avg
§102
5.6%
-34.4% vs TC avg
§112
0.7%
-39.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 666 resolved cases

Office Action

§102
Notice of AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Specification The disclosure is objected to because of the following informalities: element 132 from Figure 1 has not been described in the specification. It is not clear whether the Figure is prior art Figure. Appropriate correction is required. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a redistribution line” … “a passivation layer over the redistribution line, wherein a bottommost surface of the passivation layer is below the bottommost surface of the redistribution line” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-9 and 11-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 of U.S. Patent No. US 11,114,395 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the parent patent renders obvious the instant application. Regarding independent claim 1: Lin teaches (Claims 1-9) an integrated circuit (IC) device comprising: a redistribution line over a substrate, wherein a first angle between a topmost surface of the redistribution line and a sidewall of the redistribution line is within a first angle range, a second angle between a bottommost surface of the redistribution line and the sidewall of the redistribution line is within a second angle range, and the second angle range is different from the first angle range; a passivation layer over the redistribution line, wherein a bottommost surface of the passivation layer is below the bottommost surface of the redistribution line (Claim 1). Regarding claim 2: Lin teaches the claim limitation of the IC device of claim 1, on which this claim depends, wherein a sum of the first angle and the second angle is 180-degrees (Claim 1). Regarding claim 3: Lin teaches the claim limitation of the IC device of claim 1, on which this claim depends, wherein the second angle range ranges from 75-degrees to 85-degrees (Claim 2). Regarding claim 4: Lin teaches the claim limitation of the IC device of claim 1, on which this claim depends, wherein the first angle range ranges from 95-degrees to 105-degrees (Claim 7). Regarding claim 6: Lin teaches the claim limitation of the IC device of claim 1, on which this claim depends, wherein the passivation layer comprises a plurality of dielectric layers (Claim 2). Regarding claim 7: Lin teaches the claim limitation of the IC device of claim 6, on which this claim depends, wherein a thickness of a first dielectric layer of the plurality of dielectric layers is different from a thickness of a second dielectric layer of the plurality of dielectric layers (Claim 2). Regarding independent claim 1: Lin teaches (Claims 10-15) an integrated circuit (IC) device comprising: a redistribution line over a substrate, wherein a first angle between a topmost surface of the redistribution line and a sidewall of the redistribution line is within a first angle range, a second angle between a bottommost surface of the redistribution line and the sidewall of the redistribution line is within a second angle range, and the second angle range is different from the first angle range; a passivation layer over the redistribution line, wherein a bottommost surface of the passivation layer is below the bottommost surface of the redistribution line (Claim 10). Regarding claim 5: Lin teaches the claim limitation of the IC device of claim 1, on which this claim depends, wherein the redistribution line has a trapezoidal shape (Claim 13). Regarding independent claim 8: Lin teaches (e.g., Claims 16-20) an integrated circuit (IC) device comprising: a first redistribution line over a substrate, wherein a first angle between a topmost surface of the redistribution line and a sidewall of the redistribution line is within a first angle range, a second angle between a bottommost surface of the redistribution line and the sidewall of the redistribution line is within a second angle range, and the second angle range is different from the first angle range; a second redistribution line over the substrate; and a passivation layer over the first redistribution line and the second redistribution line, wherein the passivation layer comprises: a first layer over the first redistribution line and the second redistribution line, wherein the first layer has a first thickness; and a second layer over the first layer, wherein the second layer has a second thickness, and a ratio of the first thickness to the second thickness is equal to or greater than 75% (Claim 18). Regarding claim 9: Lin teaches the claim limitation of the IC device of claim 8, on which this claim depends, wherein a bottommost surface of the passivation layer is closer to the substrate than a bottommost surface of the first redistribution line (Claim 16). Regarding independent claim 8: Lin teaches (e.g., Claims 10-14) an integrated circuit (IC) device comprising: a first redistribution line over a substrate, wherein a first angle between a topmost surface of the redistribution line and a sidewall of the redistribution line is within a first angle range, a second angle between a bottommost surface of the redistribution line and the sidewall of the redistribution line is within a second angle range, and the second angle range is different from the first angle range; a second redistribution line over the substrate; and a passivation layer over the first redistribution line and the second redistribution line, wherein the passivation layer comprises: a first layer over the first redistribution line and the second redistribution line, wherein the first layer has a first thickness; and a second layer over the first layer, wherein the second layer has a second thickness, and a ratio of the first thickness to the second thickness is equal to or greater than 75% (Claim 10). Regarding claim 11: Lin teaches the claim limitation of the IC device of claim 8, on which this claim depends, wherein each of the first redistribution line and the second redistribution line has a trapezoidal shape (Claim 13). Regarding claim 12: Lin teaches the claim limitation of the IC device of claim 8, on which this claim depends, further comprising an insulating layer between the substrate and the first redistribution line (Claim 11). Regarding claim 13: Lin teaches the claim limitation of the IC device of claim 12, on which this claim depends, wherein the insulating layer has a variable thickness (Claim 12). Regarding claim 14: Lin teaches the claim limitation of the IC device of claim 12, on which this claim depends, further comprising an interconnect structure between the insulating layer and the substrate (Claim 14). Claims 8, 10, and 15-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. Patent No. US 10,453,811 B2 to Lin et al. Regarding independent claim 8: Lin teaches (e.g., Claims 1-10) an integrated circuit (IC) device comprising: a first redistribution line over a substrate, wherein a first angle between a topmost surface of the redistribution line and a sidewall of the redistribution line is within a first angle range, a second angle between a bottommost surface of the redistribution line and the sidewall of the redistribution line is within a second angle range, and the second angle range is different from the first angle range; a second redistribution line over the substrate; and a passivation layer over the first redistribution line and the second redistribution line, wherein the passivation layer comprises: a first layer over the first redistribution line and the second redistribution line, wherein the first layer has a first thickness; and a second layer over the first layer, wherein the second layer has a second thickness, and a ratio of the first thickness to the second thickness is equal to or greater than 75% (Claim 9). Regarding independent claim 8: Lin teaches (e.g., Claims 11-17) an integrated circuit (IC) device comprising: a first redistribution line over a substrate, wherein a first angle between a topmost surface of the redistribution line and a sidewall of the redistribution line is within a first angle range, a second angle between a bottommost surface of the redistribution line and the sidewall of the redistribution line is within a second angle range, and the second angle range is different from the first angle range; a second redistribution line over the substrate; and a passivation layer over the first redistribution line and the second redistribution line, wherein the passivation layer comprises: a first layer over the first redistribution line and the second redistribution line, wherein the first layer has a first thickness; and a second layer over the first layer, wherein the second layer has a second thickness, and a ratio of the first thickness to the second thickness is equal to or greater than 75% (Claim 17). Regarding claim 10: Lin teaches the claim limitation of the IC device of claim 8, on which this claim depends, wherein a distance between the first redistribution line and the second redistribution line is equal or greater than 1 micron (µm) (Claim 17). Regarding independent claim 15: Lin teaches (Claims 11-17) an integrated circuit (IC) device comprising: an insulating layer over a substrate, wherein the insulating layer comprises a plurality of upper surfaces and a recessed surface between adjacent upper surfaces of the plurality of upper surfaces, and the recessed surface is closer to the substrate than any of the plurality of upper surfaces; and a first redistribution line a first upper surface of the plurality of upper surfaces, wherein a first angle between a topmost surface of the redistribution line and a sidewall of the redistribution line is within a first angle range, a second angle between a bottommost surface of the redistribution line and the sidewall of the redistribution line is within a second angle range, and the second angle range is different from the first angle range (Claim 13). Regarding claim 16: Lin teaches the claim limitation of the IC device of claim 15, on which this claim depends, further comprising a passivation layer over the first redistribution line (Claim 11). Regarding claim 17: Lin teaches the claim limitation of the IC device of claim 16, on which this claim depends, wherein the passivation layer directly contacts the recessed surface of the insulating layer (Claim 16). Regarding claim 18: Lin teaches the claim limitation of the IC device of claim 17, on which this claim depends, wherein the passivation layer comprises a plurality of dielectric layers (16). Regarding claim 19: Lin teaches the claim limitation of the IC device of claim 18, on which this claim depends, wherein a thickness of a first dielectric layer of the plurality of dielectric layers is different from a thickness of a second dielectric layer of the plurality of dielectric layers (Claim 17). Regarding claim 20: Lin teaches the claim limitation of the IC device of claim 16, on which this claim depends, wherein a sum of the first angle and the second angle is 180-degrees (Claim 13). Regarding independent claim 1: Lin teaches (Claims 1-9) an integrated circuit (IC) device comprising: a redistribution line over a substrate, wherein a first angle between a topmost surface of the redistribution line and a sidewall of the redistribution line is within a first angle range, a second angle between a bottommost surface of the redistribution line and the sidewall of the redistribution line is within a second angle range, and the second angle range is different from the first angle range; a passivation layer over the redistribution line, wherein a bottommost surface of the passivation layer is below the bottommost surface of the redistribution line Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2, 6-7 and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu et al. (US 2013/0134596 A1). Regarding independent claim 1: Hu teaches (e.g., Figs. 2A-2G) an integrated circuit (IC) device comprising: a redistribution line ([0018] and [0023]: 206/232) over a substrate ([0017]: 201), wherein a first angle between a topmost surface of the redistribution line (Fig. 2H; top surface of 206/232) and a sidewall of the redistribution line is within a first angle range (sidewall portion of 206/232 is the slanted), a second angle between a bottommost surface of the redistribution line ([0018] and [0023]: 206/232) and the sidewall of the redistribution line is within a second angle range ([0018] and [0023]: angle formed by bottommost surface and the sidewall of 206/232), and the second angle range is different from the first angle range (Fig. 2G; indicates different angles); a passivation layer ([0016] and [0024]: passivation layer is a multilayer 212/242/208) over the redistribution line, wherein a bottommost surface of the passivation layer (212/242/208) is below the bottommost surface of the redistribution line (206/232). Regarding claim 2: Hu teaches the claim limitation of the IC device of claim 1, on which this claim depends, wherein a sum of the first angle and the second angle is 180-degrees (Fig. 2G shows that the first angle and the second angle is 180-degrees because both the topmost portion and the bottommost portion are horizontal and the they both have the same angle with respect to their sidewalls). Regarding claim 6: Hu teaches the claim limitation of the IC device of claim 1, on which this claim depends, wherein the passivation layer comprises a plurality of dielectric layers ([0016] and [0024]: passivation layer is a multilayer 212/242/208). Regarding claim 7: Hu teaches the claim limitation of the IC device of claim 6, on which this claim depends, wherein a thickness of a first dielectric layer of the plurality of dielectric layers is different from a thickness of a second dielectric layer of the plurality of dielectric layers ([0016] and [0024]: the thickness of the first dielectric layer 242 is different from the thickness of the second dielectric layer 212). Regarding independent claim 15: Hu teaches (e.g., Figs. 2A-2G) an integrated circuit (IC) device comprising: an insulating layer (Fig. 2A; [0017]: 208) over a substrate ([0017]: 201), wherein the insulating layer comprises a plurality of upper surfaces (Fig. 2A, top portions on left side and right side of insulating layer 212) and a recessed surface (Fig. 2A, middle portion exposing RDL layer 206, [0017]) between adjacent upper surfaces of the plurality of upper surfaces, and the recessed surface is closer to the substrate (201) than any of the plurality of upper surfaces (the recess portion is necessarily lower since it has been recessed from the upper portion to a lower portion, thus, it is closer to the substrate, as shown in Fig. 2A); and a first redistribution line ([0018] and [0023]: 206/232) a first upper surface of the plurality of upper surfaces, wherein a first angle between a topmost surface of the redistribution line (Fig. 2H; top surface of 206/232) and a sidewall of the redistribution line (sidewall portion of 206/232 is the slanted) is within a first angle range, a second angle between a bottommost surface of the redistribution line ([0018] and [0023]: 206/232) and the sidewall of the redistribution line is within a second angle range ([0018] and [0023]: angle formed by bottommost surface and the sidewall of 206/232), and the second angle range is different from the first angle range (Fig. 2G; indicates different angles). Regarding claim 16: Hu teaches the claim limitation of the IC device of claim 15, on which this claim depends, further comprising a passivation layer ([0016] and [0024]: passivation layer is a multilayer 212/242) over the first redistribution line (206/232). Regarding claim 17: Hu teaches the claim limitation of the IC device of claim 16, on which this claim depends, wherein the passivation layer (212/242) directly contacts the recessed surface of the insulating layer (208). Regarding claim 18: Hu teaches the claim limitation of the IC device of claim 17, on which this claim depends, wherein the passivation layer comprises a plurality of dielectric layers ([0016] and [0024]: passivation layer is a plurality of dielectric layers 212/242). Regarding claim 19: Hu teaches the claim limitation of the IC device of claim 18, on which this claim depends, wherein a thickness of a first dielectric layer of the plurality of dielectric layers is different from a thickness of a second dielectric layer of the plurality of dielectric layers ([0016] and [0024]: the thickness of the first dielectric layer 242 is different from the thickness of the second dielectric layer 212). Regarding claim 20: Lin teaches the claim limitation of the IC device of claim 16, on which this claim depends, wherein a sum of the first angle and the second angle is 180-degrees (Fig. 2G shows that the first angle and the second angle is 180-degrees because both the topmost portion and the bottommost portion are horizontal and the they both have the same angle with respect to their sidewalls). Allowable Subject Matter Claims 3-5 and 8-14 are objected to as having allowable subject matter and would be allowable if the outstanding ODP rejection is overcome and any art rejected limitation is overcome, including objection to the drawing. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 8: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, an integrated circuit (IC) device comprising: “a second redistribution line over the substrate; and a passivation layer over the first redistribution line and the second redistribution line, wherein the passivation layer comprises: a first layer over the first redistribution line and the second redistribution line, wherein the first layer has a first thickness; and a second layer over the first layer, wherein the second layer has a second thickness, and a ratio of the first thickness to the second thickness is equal to or greater than 75%”. Claims 9-14 depend from claim 8, and therefore, are allowable for the same reason as claim 8. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812
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Prosecution Timeline

Nov 13, 2023
Application Filed
Mar 30, 2026
Non-Final Rejection mailed — §102 (current)

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
95%
With Interview (+4.2%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 666 resolved cases by this examiner. Grant probability derived from career allowance rate.

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