Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I in the reply filed on 03/16/26 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 9-10 and 12-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshihara, US 2021/0193592.
Yoshihara shows the invention as claimed including a power module package A10 comprising:
a substrate 10 (see paragraph 0065) including a patterned metal layer 20-22 disposed thereon;
a first plurality of semiconductor die 40A disposed on a first portion 20A of the patterned metal layer, the first plurality of semiconductor die including a first plurality of power transistors that are linearly arranged along a first axis;
a second plurality of semiconductor die 40B disposed on a second portion 20B of the patterned metal layer, the second plurality of semiconductor die including a second plurality of power transistors that are linearly arranged along a second axis parallel to the first axis;
a first plurality of conductive clips 52A respectively coupling the first plurality of power transistors 40A with a third portion 21A of the patterned metal layer disposed between the first portion of the patterned metal layer and the second portion of the patterned metal layer, the third portion of the patterned metal layer being arranged along a third axis that is parallel with the first and second axis; and
a second plurality of conductive clips 52B respectively coupling the second plurality of power transistors 40B with a fourth portion 21B of the patterned metal layer disposed between the second portion of the patterned metal layer and the third portion of the patterned metal layer, the fourth portion of the patterned metal layer being arranged along a third axis that is parallel with the first, second, and third axis (see paragraphs 0117-0138).
Concerning dependent claim 10, note that Yoshihara further discloses: a plurality of power terminals (31,32) arranged on a first edge of the power module package, the first edge being parallel to the first axis and the second axis; and a switch node terminal arranged on a second edge of the power module package, the second edge being opposite and parallel to the first edge (see figs. 4 and 10 and their descriptions).
Regarding dependent claim 12, note that Yoshihara discloses the first plurality of power transistors are respective high-side transistors of a half-bridge circuit including first respective power metal-oxide-semiconductor field-effect transistors; and the second plurality of power transistors are respective low-side transistors of the half-bridge circuit including second respective power MOSFETs (see paragraph 0062).
Concerning dependent claim 13, note that Yoshihara discloses the power module package wherein: respective drain terminals of the first respective power MOSFETs are coupled with the first portion of the patterned metal layer; respective source terminals 52a,52b of the first respective power MOSFETs are coupled with the third portion of the patterned metal layer via the first plurality of conductive clips; respective drain terminals of the second respective power MOSFETs are coupled with the second portion of the patterned metal layer; and respective source terminals of the second respective power MOSFETs are coupled with the fourth portion of the patterned metal layer vias the second plurality of conductive clips (see, for example, Figs. 11-16 and paragraph 0084).
With respect to dependent claim 14, Yoshihara further discloses: a high-side source sense signal lead (note positive terminal 31); a first bond wire 54A coupling the low-side source sense signal lead with the second plurality of conductive clips; a high-side gate terminal signal lead; and a second bond wire coupling with the low-side gate terminal signal lead with respective gate terminals of the first respective power MOSFETs (see Figs. 3 and 19 and their descriptions).
Concerning dependent claim 15, Yoshihara discloses a low-side source sense signal lead (note negative terminal 32); a first bond wire 54A coupling the low-side source sense signal lead with the second plurality of conductive clips; a low-side gate terminal signal lead; and a second bond wire coupling with the low-side gate terminal signal lead with respective gate terminals of the first respective power MOSFETs (see Figs. 3 and 23 and their descriptions).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-8 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshihara, US 2021/0193592 in view of Hayashiguchi, US 2022/0254758.
Yoshihara shows the invention as claimed including a power module package A10 comprising:
A ceramic layer (see paragraph 0064) having a first primary surface and a second primary surface opposite the first primary surface; and
A patterned metal layer 10 disposed on the first primary surface;
A first plurality of semiconductor die 40A disposed on a first portion 20A of the patterned metal layer, the first plurality of semiconductor die being linearly arranged along a first axis;
A second plurality of semiconductor die 40B disposed on a second portion 20B of the patterned metal layer, the second plurality of semiconductor die being linearly arranged along a second axis parallel to the first axis;
A plurality of power terminals 31,32 arranged on a first edge of the power module package, the first edge being parallel to the first axis and the second axis;
A switch node terminal 33 arranged on a second edge of the power module package, the second edge being opposite and parallel to the first edge;
A first plurality of signal pins 36 located on a third edge of the power module package that is orthogonal to the first edge and the second edge; and
A second plurality of signal pins (also 36) (see fig. 4 and paragraphs 0061-0113).
Yoshihara does not expressly disclose the second plurality of signal pins being located on a fourth edge of the power module package, the fourth edge being opposite and parallel to the third edge. Hayashiguchi discloses a power module package where signal pins are located on opposing sides of a power module package (see fig. 10 and its description). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Yoshihara so as to have signal pins on opposing side of a package because Hayashiguchi shows this as a suitable means to connect power signals.
With respect to dependent claim 2, note that Yoshihara discloses wherein: the substrate further includes a metal layer 69 disposed on the second primary surface; and the power module package further comprises a molding compound 60 encapsulating the first plurality of semiconductor die and the second plurality of semiconductor die, and partially encapsulating the substrate, the metal layer being exposed through the molding compound (see figures 5 and 9 and their description, and paragraph 0098).
Concerning dependent claim 3, note that Yoshihara discloses wherein the plurality of power terminals (31,32) and the switch node terminal are exposed through a first primary surface of the molding compound (see figs. 2, 5, and 10 and their descriptions).
With respect to dependent claim 4, note that Yoshihara discloses wherein the first primary surface of the molding compound is located on a side of the substrate corresponding with the first primary surface of the substrate.
As to dependent claim 5, note that Yoshihara discloses wherein the metal layer is exposed through the molding compound on a second primary surface of the molding compound opposite the first primary surface of the molding compound.
Regarding dependent claims 6-7, Yoshihara discloses a leadframe, the first and second plurality of signal pins being included or coupled in the leadframe (see paragraph 0098, for example).
As to dependent claim 8, Yoshihara discloses a first plurality of conductive clips 52A respectively coupling the first plurality of semiconductor die 40A with a third portion 21A of the patterned metal layer disposed between the first portion of the patterned metal layer and the second portion of the patterned metal layer, the third portion of the patterned metal layer being arranged along a third axis that is parallel with the first and second axis; and a second plurality of conductive clips 52B respectively coupling the second plurality of semiconductor die 40B with a fourth portion 21B of the patterned metal layer disposed between the second portion of the patterned metal layer and the third portion of the patterned metal layer, the fourth portion of the patterned metal layer being arranged along a third axis that is parallel with the first, second, and third axis (see paragraphs 0117-0138).
With respect to dependent claim 11, Yoshihara is applied as above and additionally discloses a first plurality of signal pins 36 located on a third edge of the power module package that is orthogonal to the first edge and the second edge; and
A second plurality of signal pins (also 36) (see fig. 4 and paragraphs 0061-0113).
Yoshihara does not expressly disclose the second plurality of signal pins being located on a fourth edge of the power module package, the fourth edge being opposite and parallel to the third edge. Hayashiguchi discloses a power module package where signal pins are located on opposing sides of a power module package (see fig. 10 and its description). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Yoshihara so as to have signal pins on opposing side of a package because Hayashiguchi shows this as a suitable means to connect power signals.
Allowable Subject Matter
Claims 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art, either singly or in combination, fails to anticipate or render obvious, the limitations of: a positive power supply terminal coupled with the first portion of the patterned metal layer; a negative power supply terminal coupled with the fourth portion of the patterned metal layer and the third portion of the patterned metal layer, as required by dependent claim 16.
Claim 21 is allowed.
The following is a statement of reasons for the indication of allowable subject matter: the prior art, either singly or in combination, fails to anticipate or render obvious, the limitations of: at least one first power tab coupled to the substrate by at least one first pillar and extending over a first edge of the substrate, the first edge parallel to the first row and the second row; at least one second power tab coupled to the substrate by at least one second pillar and extending over a second edge of the substrate opposite the first edge; a plurality of first leads coupled to the substrate and extending over a third edge of the substrate; a plurality of second leads coupled to the substrate and extending over a fourth edge of the substrate opposite the third edge; and molding compound encapsulating the substrate, wherein the at least one first power tab and the at least one second power tab are exposed through the molding compound, as required by independent claim 21.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2009/0231810, US 2013/0020694, and US 2014/0167248 disclose the state of the art in power module packaging.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
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/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
May 21, 2026
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