Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 were rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 1 recites, inter alia, “ a first insulation layer disposed over the first surface of the substrate, and defining a first through hole extending through the first insulation layer, wherein the first through hole has a first width; a second insulation layer disposed on the first insulation layer and defining a second through hole extending through the second insulation layer, wherein the second through hole has a second width, and a difference between the first width and the second width is less than one tenth of the first width; and an electrical contact disposed in the first through hole and the second through hole, and electrically connected to the first surface of the substrate; wherein the recess portion has a third width less than the first width, and the third width is less than the second width”. It seems that the first through hole, the second through hole and the third through hole all have varying widths at different depths (Figs. 1-9). It is not clear which width the Applicant is referring to, i.e., at what depth of each hole and the recess the widths are measured. Some of the limitations of claim 1 may not be even true if the widths are measured at arbitrary depths. Appropriate correction/clarification is requested. Claims 2-9 inherit the 35 U.S.C. 112(b) or 35 U.S.C. 112, 2nd paragraph (pre-AIA ) rejections based on their dependencies on claim 1.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of Patent No. US 12,538,790 B2. Although the claims at issue are not identical, they are not patentably distinct from each other.
Regarding Claim 1, Patent No.: US 12,538,790 B2 discloses an electrical structure, comprising:
a substrate having a recess portion recessed from a first surface of the substrate (claims 1 & 10);
a first insulation layer disposed over the first surface of the substrate, and defining a
first through hole extending through the first insulation layer, wherein the first through hole has a
first width (claims 1 & 10);
a second insulation layer disposed on the first insulation layer and defining a second
through hole extending through the second insulation layer, wherein the second through hole has a second width, and a difference between the first width and the second width is less than one tenth of the first width (claims 1 & 10); and
an electrical contact disposed in the first through hole and the second through hole, and
electrically connected to the first surface of the substrate claims 1 & 10);
wherein the recess portion has a third width less than the first width, and the third width is less than the second width (claims 1 & 10).
Regarding Claim 2, Patent No.: US 12,538,790 B2, as applied to claim 1, discloses the electrical structure, wherein the first through hole is communicated with the second through hole claims 1 & 10).
Regarding Claim 3, Patent No.: US 12,538,790 B2, as applied to claim 1, discloses the electrical structure, wherein the electrical contact is a monolithic structure hole (claims 2 & 12).
Regarding Claim 4, Patent No.: US 12,538,790 B2, as applied to claim 1, discloses the electrical structure, further comprising a first metal- oxide-semiconductor (MOS) transistor and a second MOS transistor disposed on the substrate, wherein the electrical contact is disposed between the first MOS transistor and the second MOS transistor (claims 4 & 13).
Regarding Claim 5, Patent No.: US 12,538,790 B2, as applied to claim 4, discloses the electrical structure, wherein the electrical contact electrically connects an electrode of the first MOS transistor and/or the second MOS transistor (claims 5 & 14).
Regarding Claim 6, Patent No.: US 12,538,790 B2, as applied to claim 1, discloses the electrical structure, wherein a material of the second insulation layer is different from a material of the first insulation layer (claims 1 & 10).
Regarding Claim 7, Patent No.: US 12,538,790 B2, as applied to claim 1, discloses the electrical structure, wherein the substrate defines a recess portion in communication with the first through hole, and the electrical contact is further disposed in the recess portion (claims 1 & 10).
Regarding Claim 8, Patent No.: US 12,538,790 B2, as applied to claim 7, discloses the electrical structure, wherein the substrate includes a low resistance layer disposed on a bottom wall of the recess portion (claim 8).
Regarding Claim 9, Patent No.: US 12,538,790 B2, as applied to claim 8, discloses the electrical structure, wherein the substrate includes silicon, and the low resistance layer includes cobalt disilicide (CoSi2) (claim 3 together with claim 9).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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07/19/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893
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