Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
OFFICE ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) The claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Quayle (US 2005/0114113)
Regarding claim 1, the prior art discloses:
A computer-based method, comprising:
simulating a circuit design (title) and a co-simulation model (par 8:
simulation is controlled by the designer in interactive operation. Designers can run simulation…) configured to model circuitry that operates in coordination with a hardware implementation (par 2-13 or fig 2-3) of the circuit design, wherein the simulating includes:
in response to a request for a data transfer (see one or more of title, abstract, FIELD OF INVENTION) received by the co-simulation model from the circuit design, providing, from the co-simulation model, a ready signal (read/write initiation burst transfer, read/write status flag, data ready (fig 2-3, 6, par 35-36) to the circuit design after a first predetermined number of simulation clock cycles (see at least par 9-10, fig 5) corresponding to an initiation interval of the circuitry modeled by the co-simulation model; and
in response to receiving state information for the data transfer, providing a response (see at least par 10-14, 56) from the co-simulation model to the circuit design after a second predetermined number of simulation clock cycles (see at least par 9-10, fig 5) corresponding to a response time of the circuitry modeled by the co-simulation model.
(Claim 2) wherein the second predetermined number of simulation clock cycles (par 9-10, fig 5) is measured from receipt of the state information by the co-simulation model.
(Claim 3) wherein the circuitry modeled by the co-simulation model includes a memory controller and a memory coupled to the memory controller (fig 1-4, 6).
(Claim 4) wherein the co-simulation model includes a sequencer (see one or more of abstract, summary, fig 2-3) and a plurality of drivers (see one or more of abstract, summary par 13, fig 2-6) forming a communication bus interface of a communication bus between the co-simulation model and the circuit design.
(Claim 5) wherein one or more of the plurality of drivers are configured to count the first predetermined number of simulation clock cycles (par 9-10, fig 5).
(Claim 6) wherein the sequencer (see one or more of abstract, summary, fig 2-3) is configured to count the second predetermined number of simulation clock cycles.
(Claim 7) wherein the data transfer is a read operation (fig 1-4, 6) , the request includes assertion of a valid signal of a read address-control channel, and the response includes data read from an array of the co-simulation model (fig 1-4, 6).
(Claim 8) wherein the data transfer is a write operation (fig 1-4, 6) and the request includes assertion of a valid signal of a write address-control channel and assertion of a valid signal of a write data channel (fig 1-4, 6)
(Claim 9) wherein the response is a valid signal asserted on a write response channel (fig 1-4, 6)
Claims 10-20 recite similar subject matter and are rejected for the same reason.
Claims 1, 10, 19 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Vo (US 2015/0356219)
Regarding claim 1, the prior art discloses:
A computer-based method, comprising:
simulating a circuit design and a co-simulation model configured to model circuitry that operates in coordination with a hardware implementation of the circuit design (abstract, summary) , wherein the simulating includes:
in response to a request for a data transfer received by the co-simulation model from the circuit design (par 29-36), providing, from the co-simulation model, a ready signal (par 19, 29, 36), to the circuit design after a first predetermined number of simulation clock cycles (par 36, claim 7) corresponding to an initiation interval of the circuitry modeled by the co-simulation model; and
in response to receiving state information for the data transfer, providing a response from the co-simulation model to the circuit design (summary, fig 1) after a second predetermined number of simulation clock cycles (par 36, claim 7) corresponding to a response time of the circuitry modeled by the co-simulation model (summary, fig 1-2).
Claims 10, 19 recite similar subject matter and are rejected for the same reason.
Claims 1-20 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Bowen (US 2003/0105620)
Regarding claim 1, the prior art discloses:
A computer-based method, comprising:
simulating a circuit design and a co-simulation model (see one or more of fig 39, 41-44 and/or par 48, 51-58, 2241) configured to model circuitry that operates in coordination with a hardware implementation (see one or more of FIELD OF INVENTION, fig 1, 39, par 48, 50) of the circuit design, wherein the simulating includes:
in response to a request for a data transfer received by the co-simulation model from the circuit design (par 2265-2267, 2288, 2203-2206, 2213, 2253-2254), providing, from the co-simulation model, a ready signal (see one or more of par 7036-7047, 7057, 7279, 7289, fig 79-81) to the circuit design after a first predetermined number of simulation clock cycles corresponding to an initiation interval of the circuitry modeled by the co-simulation model (fig 42, 57-59); and
in response to receiving state information for the data transfer, providing a response (par 2184, 2213, 2373-2275) from the co-simulation model to the circuit design after a second predetermined number of simulation clock cycles (fig 42, 57-59) corresponding to a response time of the circuitry modeled by the co-simulation model.
(Claim 2) wherein the second predetermined number of simulation clock cycles is measured from receipt of the state information by the co-simulation model (fig 57-59).
(Claim 3) wherein the circuitry modeled by the co-simulation model includes a memory controller and a memory coupled to the memory controller (par 7265, fig 64-65, 78, 83).
(Claim 4) wherein the co-simulation model includes a sequencer (par 163, 582, 2175) and a plurality of drivers forming a communication bus interface (simulator interface/GUI /API , two-side interface-simulator side and co-simulation side, Application Programmers Interface (API) to write a plugin which can be co-simulated (par 8, 1565, 1829, 2189, 2199, 2241, 4716, 5189, 5198, 5391, 5393) of a communication bus between the co-simulation model and the circuit design.
(Claim 5) wherein one or more of the plurality of drivers are configured to count the first predetermined number of simulation clock cycles (fig 57-59).
(Claim 6) wherein the sequencer is configured to count the second predetermined number of simulation clock cycles (fig 57-59).
(Claim 7) wherein the data transfer is a read operation, the request includes assertion of a valid signal of a read address-control channel (fig 62-81), and the response includes data read from an array of the co-simulation model (fig 62-81).
(Claim 8) wherein the data transfer is a write operation and the request includes assertion of a valid signal of a write address-control channel and assertion of a valid signal of a write data channel (fig 62-81)
(Claim 9) wherein the response is a valid signal asserted on a write response channel (gig 62-81).
Claims 10-20 recite similar subject matter and are rejected for the same reason.
Correspondence Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL DINH whose telephone number is 571-272-1890. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s Supervisor, Jack Chiang can be reached on 571-272-7483. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAUL DINH/ Primary Examiner, Art Unit 2851
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