DETAILED ACTION
This correspondence is in response to the communications received 05/04/2026. Claims 21-26 have been added. Claims 15-20 have been canceled. Claims 1-14 and 21-26 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-14 and 21-26 in the reply filed on 05/04/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 11/14/2023 and 12/09/2024 have been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 11 and 21 both require “a TSV”. While claim 1 introduces the non-abbreviated version, “through substrate via”, claims 11 and 21 are separate independent claims that should also include the non-abbreviated version in addition to “a TSV” for clarity.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
PNG
media_image1.png
566
873
media_image1.png
Greyscale
PNG
media_image2.png
564
846
media_image2.png
Greyscale
Regarding claim 1, a device, comprising:
a semiconductor substrate (131-1) comprising a first side (131a) and a second side (131b)opposite to the first side (see Fig. 1A); and
a through substrate via (TSV) (135) comprising a first portion (1351) and a second portion (1352) stacked upon and connected to the first portion (see Fig. 1G), the first portion extending through the first side of the semiconductor substrate, the second portion extending through the second side of the semiconductor substrate (see Fig. 1G), and an aspect ratio of the first portion being greater than that of the second portion (see Fig. 1G, and "the aspect ratio (H1/D1) of the first portion 1351 is greater than (or substantially equal to) the aspect ratio (H2/D2) of the second portion 1352", [0032]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-6, 8, 9, and 21-26 are rejected under 35 U.S.C. 103 as being unpatentable over Sheng et al. (US 20250329588 A1, filed 11/04/2022) in view of Kirby et al. (US 9,449,906 B2, published 09/20/2016).
PNG
media_image3.png
377
613
media_image3.png
Greyscale
PNG
media_image4.png
419
754
media_image4.png
Greyscale
Regarding claim 1, Figs. 1-9 of Sheng disclose a device (Sheng does not specifically disclose a device, however, a secondary reference will be utilized to teach this limitation below), comprising:
a semiconductor substrate (“semiconductor base 100”, [0056], where “The semiconductor base 100 may include a semiconductor substrate, which is, for example, a silicon substrate, a germanium (Ge) base, a silicon germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate or the like”, [0056]) comprising a first side (as seen in Fig. 9, the upper side of 100 is a first side denoted as the “front side 100a”, [0055], seen in Fig. 2) and a second side (as seen in Fig. 4B, the lower side of 100 is a second side denoted as the “backside 100b”, [0055], seen in Fig. 2) opposite to the first side (as seen in Fig. 9, the upper side of 100 is opposite to the lower side of 100); and
a through substrate via (TSV) (together “backside via 110”, [0060], “front-side via 130”, [0077], and “rewiring via 141”, [0090] form a TSV as they extend through 100 thus forming a “high aspect ratio TSV”, [0093]) comprising a first portion (together 130 and 141 are a first portion) and a second portion (110 is a second portion) stacked upon and connected to the first portion (as seen in Fig. 9, depending on the perspective of 100, 110 is stacked upon and connected to 130, one having ordinary skill in the art would recognize that during manufacturing it is common to reorient the work piece depending on the process being carried out), the first portion extending through the first side of the semiconductor substrate (as seen in Fig. 9, 130 extends through the upper side of 100), the second portion extending through the second side of the semiconductor substrate (as seen in Fig. 9, 110 extends through the lower side of 100), and an aspect ratio of the first portion being greater than that of the second portion (as seen in Fig. 9, 130 and 141 are together of approximately equal height as 110 and have a smaller width than 110, thus 130 and 141 have a greater aspect ratio than that of 110).
Sheng fails to disclose “a device”.
However, in a similar field of endeavor, Figs. 1-14 of Kirby teach a device (“FIGS. 1-14 are partially schematic cross-sectional views illustrating a portion of a semiconductor device 100 in a method for making through-substrate vias or other connectors in accordance with an embodiment of the present technology ... As shown in FIG. 1, the semiconductor device 100 can include a substrate 102, an electrical component 104 (shown schematically), and an electrode 106 extending from the electrical component 104 through a dielectric region 108. The electrical component 104 can be a transistor (e.g., a bipolar or field-effect transistor), a diode, a capacitor, or another suitable solid-state component formed in and/or on the substrate 102”, col. 3, lines 27-40, thus the TSV of Sheng can be integrated into a substrate with an electrical component thereby forming a device).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a device” as taught by Kirby in the system of Sheng for the purpose of increasing electrical functionality in the TSV structure of Sheng.
PNG
media_image5.png
567
559
media_image5.png
Greyscale
Regarding claim 2, Figs. 1-9 of Sheng in combination with Figs. 1-14 of Kirby disclose the device of claim 1, Figs. 1-14 of Kirby further disclose wherein the TSV comprises a seed layer (together “first barrier/seed material 118”, col. 4, lines 53-54, and “second barrier/seed material 128”, col. 6, lines 34-35 form a seed layer), and a part of the seed layer at an interface of the first and second portions is thicker than another part of the seed layer lining an inner sidewall of the semiconductor substrate (as seen in Fig. 14, the combined thickness of 118 and 128 at the interface between “conductive material 120”, col. 4, lines 52-53, and “second conductive material 140”, col. 6, line 57, is thicker than either 118 or 128 lining an inner sidewall of 102, where 120, 140, and 102 of Kirby are equivalent to 130, 110, and 100 of Sheng respectively).
Regarding claim 3, Figs. 1-9 of Sheng in combination with Figs. 1-14 of Kirby disclose the device of claim 1, Figs. 1-14 of Kirby further disclose wherein each of the first and second portions (“conductive material 120”, col. 4, lines 52-53, and “second conductive material 140”, col. 6, line 57, are equivalent to 130 and 100 of Sheng respectively) of the TSV comprises a seed layer (together “first barrier/seed material 118”, col. 4, lines 53-54, and “second barrier/seed material 128”, col. 6, lines 34-35 form a seed layer) and a conductive material layer disposed on the seed layer (as seen in Fig. 14, 120 and 140 are disposed on 118 and 128 respectively), and the conductive material layer of the first portion is separated from the conductive material layer of the second portion through the seed layers of the first and second portions (as seen in Fig. 14, 120 is separated from 140 through 118 and 128).
Regarding claim 4, Figs. 1-9 of Sheng in combination with Figs. 1-14 of Kirby disclose the device of claim 1, Figs. 1-9 of Sheng further disclose wherein a maximum lateral dimension of the second portion of the TSV is greater than that of the first portion of the TSV (as seen in Fig. 9, a maximum lateral dimension of 110 is greater than that of 130 and 141).
Regarding claim 5, Figs. 1-9 of Sheng in combination with Figs. 1-14 of Kirby disclose the device of claim 1, Figs. 1-9 of Sheng further disclose wherein a maximum height of the first portion of the TSV is greater than or substantially equal to that of the second portion of the TSV (as seen in Fig. 9, a maximum height of 130 and 141 is greater than or substantially equal to that of 130).
Regarding claim 6, Figs. 1-9 of Sheng in combination with Figs. 1-14 of Kirby disclose the device of claim 1, Figs. 1-9 of Sheng further disclose wherein the first portion of the TSV comprises a first dielectric liner (as seen in Fig. 9, the portion of “first insulating layer 102”, [0063] surrounding 130 and 141 is a first dielectric liner as “first insulating layer 102 may include at least one of silicon oxide, silicon nitride and silicon oxynitride”, [0063], where these materials are known in the art as dielectrics), the second portion of the TSV comprises a second dielectric liner (as seen in Fig. 9, the portion of 102 surrounding 110 is a second dielectric liner) laterally offset from the first dielectric liner (as seen in Fig. 9, the portion of 102 surrounding 110 is laterally offset from the portion of 102 surrounding 130 and 141).
Regarding claim 8, Figs. 1-9 of Sheng in combination with Figs. 1-14 of Kirby disclose the device of claim 1, Figs. 1-9 of Sheng further disclose further comprising:
a dielectric layer (“second insulating layer 103”, [0069] where “second insulating layer 103 may be formed on the backside via 110. The second insulating layer 103 may include, for example, at least one of silicon oxide, silicon nitride and silicon oxynitride”, [0069], these materials are known in the art as dielectrics) overlying the second side of the semiconductor substrate (as seen in Fig. 9, 103 is overlying the lower side of 100); and
a conductive pad (“backside contact pad 120”, [0067]) covered by the dielectric layer (120 is laterally covered by 103) and connected to the second portion of the TSV (as seen in Fig. 9, 120 is connected to 110), wherein a surface of the dielectric layer away from the second side of semiconductor substrate is substantially leveled with a surface of the conductive pad away from the second portion of the TSV (as seen in Fig. 9, a surface of 103 away from the lower side of 100 is substantially leveled with a surface of the conductive pad away from 110).
Regarding claim 9, Figs. 1-9 of Sheng in combination with Figs. 1-14 of Kirby disclose the device of claim 8, Figs. 1-9 of Sheng further disclose wherein a maximum lateral dimension of the conductive pad of the TSV is greater than the maximum lateral dimension of the second portion of the TSV (as seen in Fig. 9, a maximum lateral dimension of 110 is greater than the maximum lateral dimension of 110).
Regarding claim 21, Figs. 1-9 of Sheng disclose a device (Sheng does not specifically disclose a device, however, a secondary reference will be utilized to teach this limitation below), comprising:
a semiconductor substrate (“semiconductor base 100”, [0056], where “The semiconductor base 100 may include a semiconductor substrate, which is, for example, a silicon substrate, a germanium (Ge) base, a silicon germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate or the like”, [0056]); and
a TSV (together “backside via 110”, [0060], “front-side via 130”, [0077], and “rewiring via 141”, [0090] form a TSV as they extend through 100 thus forming a “high aspect ratio TSV”, [0093]) penetrating through the semiconductor substrate (as seen in Fig. 9, 110, 130, and 141 penetrate through 100), the TSV comprising:
a first portion (together 130 and 141 are a first portion) comprising a first dielectric liner (as seen in Fig. 9, the portion of “first insulating layer 102”, [0063] surrounding 130 and 141 is a first dielectric liner as “first insulating layer 102 may include at least one of silicon oxide, silicon nitride and silicon oxynitride”, [0063], where these materials are known in the art as dielectrics); and
a second portion (110 is a second portion) connected to the first portion (as seen in Fig. 9, 110 is connected to 130), the second portion comprising a second dielectric liner (as seen in Fig. 9, the portion of 102 surrounding 110 is a second dielectric liner) offset from the first dielectric liner at an interface of the first portion and the second portion (as seen in Fig. 9, the portion of 102 surrounding 110 is offset from the portion of 102 surrounding 130 and 141 at an interface of 130 and 110), wherein a maximum lateral dimension of the first portion is less than a maximum lateral dimension of the second portion (as seen in Fig. 9, a maximum lateral dimension of 130 and 141 is less than a maximum lateral dimension of 110).
Sheng fails to disclose “a device”.
However, in a similar field of endeavor, Figs. 1-14 of Kirby teach a device (“FIGS. 1-14 are partially schematic cross-sectional views illustrating a portion of a semiconductor device 100 in a method for making through-substrate vias or other connectors in accordance with an embodiment of the present technology ... As shown in FIG. 1, the semiconductor device 100 can include a substrate 102, an electrical component 104 (shown schematically), and an electrode 106 extending from the electrical component 104 through a dielectric region 108. The electrical component 104 can be a transistor (e.g., a bipolar or field-effect transistor), a diode, a capacitor, or another suitable solid-state component formed in and/or on the substrate 102”, col. 3, lines 27-40, thus the TSV of Sheng can be integrated into a substrate with an electrical component thereby forming a device).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a device” as taught by Kirby in the system of Sheng for the purpose of electrical functionality to the TSV structure of Sheng.
Regarding claim 22, Figs. 1-9 of Sheng in combination with Figs. 1-14 of Kirby disclose the device of claim 21, Figs. 1-14 of Kirby further disclose wherein the first portion of the TSV (“conductive material 120”, col. 4, lines 52-53, where 120 of Kirby is equivalent to 130 of Sheng) comprises a first seed layer (“first barrier/seed material 118”, col. 4, lines 53-54), the second portion of the TSV (“second conductive material 140”, col. 6, line 57, where 140 of Kirby is equivalent to 110 of Sheng) comprises a second seed layer (“second barrier/seed material 128”, col. 6, lines 34-35”), the second seed layer is in contact with the first seed layer and the first dielectric liner at the interface of the first portion and the second portion (as seen in Fig. 14, 128 is in contact with 118 and “dielectric liner 114”, col. 4, line 9, at the interface of 120 and 140, where 114 of Kirby is equivalent to both portions of 102 of Sheng).
Regarding claim 23, Figs. 1-9 of Sheng in combination with Figs. 1-14 of Kirby disclose the device of claim 21, Figs. 1-9 of Sheng further disclose wherein the second dielectric liner of the second portion of the TSV comprises a first segment extending along the interface of the first portion and the second portion (as seen in Fig. 9, the portion of 102 surrounding 110 has a first horizontal segment extending along the interface of 130 and 110) and a second segment connected to the first segment and extending along a height of the second portion of the TSV (as seen in Fig. 9, the portion of 102 surrounding 110 has a second vertical segment connected to the first horizontal segment and extending along a height of 110).
Regarding claim 24, Figs. 1-9 of Sheng in combination with Figs. 1-14 of Kirby disclose the device of claim 21, Figs. 1-9 of Sheng further disclose further comprising:
an isolation layer (as seen in Fig. 9, the horizontal portion of 102 between 100 and “103 second insulating layer”, [0043], and between 100 and “120 backside contact pad”, [0043] is an isolation layer as 102 is an insulating layer that electrically isolates neighboring materials) disposed on the second side of the semiconductor substrate (as seen in Fig. 9 the horizontal portion of 102 is disposed on the lower side of 100); and
a conductive feature (120 is a conductive feature) disposed over the second side of the semiconductor substrate (as seen in Fig. 9, 120 is disposed over the lower side of 100), wherein a segment of the second portion of the TSV is protruded from the second side of the semiconductor substrate (as seen in Fig. 9, a segment of 110 is protruded from the lower side of 100) to be electrically coupled to the conductive feature (as seen in Fig. 9, the segment of 110 is connected to 120, and as both are conductive elements, they are therefore electrically coupled), and the second dielectric liner is in contact with a seed layer of the conductive feature (Sheng does not disclose a seed layer of the conductive feature, however, Kirby teaches “a first barrier/seed material 118 can be formed on the dielectric liner 114 to seed formation of the conductive material 120 and reduce diffusion of the conductive material 120 through the substrate 102”, col. 4, lines 53-57, thus a barrier/seed layer could be formed on 102 of Sheng on both the portion surrounding 110 and the horizontal portion wherein the portion of 102 surrounding 110 will be in contact with the barrier/seed layer).
Regarding claim 25, Figs. 1-9 of Sheng in combination with Figs. 1-14 of Kirby disclose the device of claim 24, Figs. 1-9 of Sheng further disclose wherein the isolation layer is disposed between the second side of the semiconductor substrate and the conductive feature (as seen in Fig. 9, the horizontal portion of 102 is disposed between the lower side of 100 and 120), and the second dielectric liner of the second portion of the TSV is laterally interfaced with the isolation layer (as seen in Fig. 9, portion of 102 surrounding 110 is laterally interfaced with the horizontal portion of 102).
Regarding claim 26, Figs. 1-9 of Sheng in combination with Figs. 1-14 of Kirby disclose the device of claim 21, Figs. 1-9 of Sheng further disclose further comprising:
a device layer disposed on the first side of the semiconductor substrate (“the semiconductor base 100 may include one or more electronic components formed in the semiconductor substrate and a front-side dielectric layer 101 covering the electronic components. The electronic components are formed at the front side 100a of the semiconductor base 100”, [0056], thus the upper portion of 100 as seen in Fig. 9 can be considered a device layer); and
an interconnect structure (“140 rewiring layer”, [0043], where “the electrical interconnect structure can provide an interconnection through the rewiring layer 140”, [0100], thus 140 serves as an interconnect structure) disposed on the device layer (as seen in Fig. 9, 140 is disposed on the upper portion of 100), wherein the first portion of the TSV extends through the device layer and into the interconnect structure (as seen in Fig. 9, 130 and 141 extend through the upper portion of 100 and into 140).
Claims 7 and 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Sheng et al. (US 20250329588 A1, filed 11/04/2022) in view of Kirby et al. (US 9,449,906 B2, published 09/20/2016) in view of Chen et al. (US 20230260977 A1, published 08/17/2023).
Regarding claim 7, Figs. 1-9 of Sheng in combination with Figs. 1-14 of Kirby disclose the device of claim 1.
Sheng in combination with Kirby fails to disclose “further comprising:
an interconnect structure below the first side of the semiconductor substrate, wherein a part of the first portion of the TSV extending through the first side of the semiconductor substrate extends further into a dielectric layer of the interconnect structure to be in contact with an interconnect trace of the interconnect structure.”
PNG
media_image6.png
554
941
media_image6.png
Greyscale
However, in a similar field of endeavor, Figs. 1A and 1B of Chen teach further comprising:
an interconnect structure (“interconnect structure 130A”, [0036]) below the first side of the semiconductor substrate (as seen in Fig. 1A, 130A is below the “first surface 124a (also referred to as “front-side surface 124a”)”, [0037], of “substrate 124”, [0037] where 124 of Chen is equivalent to 100 of Sheng and 124a of Chen is equivalent to the upper side of 100 of Sheng as seen in Fig. 9 of Sheng as both 124a and the upper side of 100 are referred to as the front side), wherein a part of the first portion of the TSV extending through the first side of the semiconductor substrate extends further into a dielectric layer of the interconnect structure to be in contact with an interconnect trace of the interconnect structure (Chen does not specifically disclose the details of 130A, however Chen does state “interconnect structures 130A and 130B can include several levels of horizontal metal lines and vertical metal vias”, [0038], and as seen in Fig. 1A, “conductive through-vias 136”, [0036] extend through 124a into an undisclosed layer to be in contact with a horizontal metal line that serves as an interconnect trace. One having ordinary skill in the art would understand that in order for 130A to function as an interconnect layer, the undisclosed layer must be an insulating or dielectric material to prevent electrical connectivity between the horizontal metal lines and vertical metal vias. Further, Chen discloses a “contact layer 132A”, [0036], where “Each of contact layers 130A and 130B can include (i) metal pads 134A and 134B similar to metal pads 122A and 122B, respectively, and (ii) passivation layers 134C and 134D”, [0038], thus a similar passivation layer could be utilized as the undisclosed layer in 130A. Kirby teaches “the first passivation material 124a is a silicon oxide”, col. 5, lines 56-57, thus the undisclosed layer of 130A of Chen can be silicon oxide which is known in the art as a dielectric material).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “further comprising:
an interconnect structure below the first side of the semiconductor substrate, wherein a part of the first portion of the TSV extending through the first side of the semiconductor substrate extends further into a dielectric layer of the interconnect structure to be in contact with an interconnect trace of the interconnect structure” as taught by Chen in the system of Sheng in combination with Kirby for the purpose of increasing the connectivity of the structure disclosed by Sheng in combination with Kirby enabling greater functionality of the device.
Regarding claim 10, Figs. 1-9 of Sheng in combination with Figs. 1-14 of Kirby disclose the device of claim 8.
Sheng in combination with Kirby fails to disclose “wherein the semiconductor substrate, the TSV, the dielectric layer, and the conductive pad are included in a semiconductor die, and the device further comprises:
a redistribution structure disposed on and electrically coupled to the semiconductor die, wherein a redistribution line of the redistribution structure is in physical and electrical contact with the conductive pad.”
However, in a similar field of endeavor, Figs. 1A and 1B of Chen teach wherein the semiconductor substrate, the TSV, the dielectric layer, and the conductive pad are included in a semiconductor die (“Second IC die 104A can include any number of semiconductor devices 126, trench capacitors 128, and conductive through-vias 136”, [0036], thus the structure disclosed by Sheng and Kirby can be incorporated into a semiconductor die), and the device further comprises:
a redistribution structure (“redistribution layer (RDL) 110”, [0028]) disposed on and electrically coupled to the semiconductor die (as seen in Fig. 1A, 108 is on 104, and “first die layer 102 can be electrically bonded to underlying second die layer 104 with redistribution layer 110 and bonding layer 112”, [0028]), wherein a redistribution line of the redistribution structure is in physical and electrical contact with the conductive pad (after combination of Chen with Sheng, 110 of Chen will be in physical and electrical contact with 120 of Sheng in order to provide electrical contact between 110 of Chen and 110, 130, and 141 of Sheng).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the semiconductor substrate, the TSV, the dielectric layer, and the conductive pad are included in a semiconductor die, and the device further comprises:
a redistribution structure disposed on and electrically coupled to the semiconductor die, wherein a redistribution line of the redistribution structure is in physical and electrical contact with the conductive pad” as taught by Chen in the system of Sheng in combination with Kirby for the purpose of increasing the connectivity of the structure disclosed by Sheng in combination with Kirby enabling greater functionality of the device.
Regarding claim 11, Figs. 1-9 of Sheng disclose a device (Sheng does not specifically disclose a device, however, a secondary reference will be utilized to teach this limitation below), comprising:
a first encapsulated die comprising (Sheng does not specifically disclose a first encapsulated die, however, a secondary reference will be utilized to teach this limitation below):
a semiconductor substrate “semiconductor base 100”, [0056], where “The semiconductor base 100 may include a semiconductor substrate, which is, for example, a silicon substrate, a germanium (Ge) base, a silicon germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate or the like”, [0056]); and
a TSV (together “backside via 110”, [0060], “front-side via 130”, [0077], and “rewiring via 141”, [0090] form a TSV as they extend through 100 thus forming a “high aspect ratio TSV”, [0093]) penetrating through the semiconductor substrate (as seen in Fig. 9, 110, 130, and 141 penetrate through 100), the TSV comprising a first portion (together 130 and 141 are a first portion) and a second portion (110 is a second portion) stacked upon and connected to the first portion (as seen in Fig. 9, depending on the perspective of 100, 110 is stacked upon and connected to 130, one having ordinary skill in the art would recognize that during manufacturing it is common to reorient the work piece depending on the process being carried out).
Sheng fails to disclose “A device, comprising:
a first encapsulated die comprising:
a portion of a seed layer of the TSV at an interface of the first and second portions being thicker than another portion of the seed layer lining an inner sidewall of the semiconductor substrate.”
However, in a similar field of endeavor, Figs. 1-14 of Kirby teach a device (“FIGS. 1-14 are partially schematic cross-sectional views illustrating a portion of a semiconductor device 100 in a method for making through-substrate vias or other connectors in accordance with an embodiment of the present technology ... As shown in FIG. 1, the semiconductor device 100 can include a substrate 102, an electrical component 104 (shown schematically), and an electrode 106 extending from the electrical component 104 through a dielectric region 108. The electrical component 104 can be a transistor (e.g., a bipolar or field-effect transistor), a diode, a capacitor, or another suitable solid-state component formed in and/or on the substrate 102”, col. 3, lines 27-40, thus the TSV of Sheng can be integrated into a substrate with an electrical component thereby forming a device), comprising:
a portion of a seed layer of the TSV (together “first barrier/seed material 118”, col. 4, lines 53-54, and “second barrier/seed material 128”, col. 6, lines 34-35 form a seed layer for “conductive material 120”, col. 4, lines 52-53, and “second conductive material 140”, col. 6, line 57 where 120 and 140, of Kirby are equivalent to 130 and 110 of Sheng respectively) at an interface of the first and second portions being thicker than another portion of the seed layer lining an inner sidewall of the semiconductor substrate (as seen in Fig. 14, the combined thickness of 118 and 128 at the interface between 120 and 140 is thicker than either 118 or 128 lining an inner sidewall of 102, where 102 of Kirby is equivalent to 100 of Shen).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a device, comprising:
a portion of a seed layer of the TSV at an interface of the first and second portions being thicker than another portion of the seed layer lining an inner sidewall of the semiconductor substrate” as taught by Kirby in the system of Sheng for the purpose of increasing electrical functionality in the TSV structure of Sheng.
Sheng in combination with Kirby fails to disclose “a first encapsulated die”.
However, in a similar field of endeavor, Figs. 1A and 1B of Chen teach first encapsulated die (“Second IC die 104A can include any number of semiconductor devices 126, trench capacitors 128, and conductive through-vias 136”, [0036], thus the structure disclosed by Sheng and Kirby can be incorporated into a semiconductor die, as seen in Fig. 1A, 104A is encapsulated by “encapsulation layer 104C”, [0035]).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a first encapsulated die” as taught by Chen in the system of Sheng in combination with Kirby for the purpose of incorporating the TSV structure of Sheng into a larger device thus enabling enhance functionality, connectivity, and physical protection.
Regarding claim 12, Figs. 1-9 of Sheng in combination with Figs. 1-14 of Kirby and Figs. 1A and 1B of Chen disclose the device of claim 11, Figs. 1-9 of Sheng further disclose wherein an aspect ratio of the first portion of the TSV is greater than or substantially equal to that of the second portion of the TSV (as seen in Fig. 9, 130 and 141 are together of approximately equal height as 110 and have a smaller width than 110, thus 130 and 141 have a greater aspect ratio than that of 110).
Regarding claim 13, Figs. 1-9 of Sheng in combination with Figs. 1-14 of Kirby and Figs. 1A and 1B of Chen disclose the device of claim 11, Figs. 1A and 1B of Chen further disclose further comprising:
a second encapsulated die (“first IC die 102A”, [0032], seen in Fig. 1A, 102A is encapsulated by “encapsulation layer 102C”, [0032]) stacked over the first encapsulated die (as seen in Fig. 1A, 102A is stacked over 104A);
a first redistribution structure (“redistribution layer (RDL) 110”, [0028]) interposed between and electrically coupled to the first and second encapsulated dies (as seen in Fig. 1a, 110 is interposed between 104A and 102A, and “In some embodiments, first die layer 102 can be electrically bonded to underlying second die layer 104 with redistribution layer 110 and bonding layer 112” [0028]).
Regarding claim 14, Figs. 1-9 of Sheng in combination with Figs. 1-14 of Kirby and Figs. 1A and 1B of Chen disclose the device of claim 13, Figs. 1A and 1B of Chen further disclose further comprising:
a second redistribution structure (“package substrate 106”, [0028], Chen does not specifically label 106 as a redistribution layer, however “Package substrate 106 can include conductive lines 106A and conductive vias 106B”, [0030] and as seen in Fig. 1A, 106A and 106B redistribute the electrical connections between “conductive bonding structures 114A”, [0029] and “conductive bonding structures 120A”, [0028], thus 106 serves as a redistribution layer) electrically coupled to the first encapsulated die through solder joints (“second die layer 104 can be electrically bonded to underlying package substrate 106 with bonding layer 114”, [0028], where “conductive bonding structures 112A and 114A can include solder bumps”, [0029]), wherein the first and second redistribution structures are disposed at opposing sides of the first encapsulated die (as seen in Fig. 1A, 110 and 106 are disposed at opposing sides of 104A).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
Prosecution Insights