DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1-20 are under consideration
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 17, it is unclear what is meant by “the first scribed line regions and the second scribed line regions define the interposer regions”, which may, for example, be interpreted as:
the scribe line regions form borders between distinct interposer regions,
each scribe line region represents a distinct interposer region, or
the scribe line regions discloses information to identify (or define) each interposer region.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-9, 11-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hu (US20190164899A1, published 2019) in view of Yu (US 20140042643 A1, published 2014).
Regarding claims 1-9, 11-16, and 18-20,
Hu teaches a method for manufacturing semiconductor devices include steps of depositing a first photoresist over a first dielectric layer, first exposing the first photoresist to a first light-exposure using a first lithographic mask, and second exposing the first photoresist to a second light-exposure using a second lithographic mask [abstract]. Hu teaches using a device wafer as a substrate [0010]. Hu teaches a semiconductor die, which may be an interposer [0012].
Hu teaches a first exposure forming a first active signal region 110A and a second exposure forming a second active signal area 110B, further forming stitching regions 110AB, 110AC, and 110AD, each of which may further contain active signal lines [0028-0031, fig 5-8], where the first and second exposure regions (first and second shot regions) are shown with the same size and alternately arranged in a first direction, reading on instant claims 3 and 11.
Examiner notes that the instant two stitching regions may include regions adjacent to one another. For example, the stitching region 110AB of Hu may comprise of a plurality of stitching regions, each of which is an overlap of the first and second exposures.
However, Hu is fails to disclose the interposer die layout, such as orientation and locations of components such as logic chip regions and memory chip regions.
Yu, analogous art, teaches a method for forming an interposer [abstract], where the interposer comprises of the logic die (chip region) which may be 301 and the memory dies (first and second memory chip regions) which may be 303 or 305 as shown below [0041, fig 3A-3D].
Yu further teaches that these and all other suitable layouts are fully intended to be included within the scope of the embodiments [0044].
As both Hu and Yu teach methods of forming an interposer die, it would have been obvious to a person of ordinary skill in the art that using an interposer die layout comprising of a logic chip region and a plurality of memory chip regions as disclosed by Yu in the interposer die of Hu would result in a comparable and functional interposer die, where the orientation and layout of the logic chip region and memory chip regions may be adjusted.
For example, the logic chip region may be located in region 110A of Hu, the first memory chip region may be located in region 110A, 810, and/or 110B of Hu, and the second memory chip region may be located in region 110A, 810, and/or 110B of Hu [0031, fig 8], reading on instant claims 1-2, 4-9, and 12-15.
Hu teaches processed wafers are then singulated into a plurality of chips, where the singulation is performed on scribe lines [0055].
It would have been obvious to a person of ordinary skill in the art that the scribe lines of Hu would align with those described in instant claim 16 in order to form the rectangular die as seen in figure 8 of Hu, further exemplified by Rahman (“A Review of A to Z of Semiconductor Fabrication.”, published 2021).
Rahman teaches scribe lines are thin, non-functional spaces between chips (die) [pages 7-8], which would include a first set of scribe line regions extending in a first direction and arranged in a second direction as well as a second set of scribe line regions extending in the second direction and arranged in the first direction, where the two directions and scribe line regions intersect perpendicularly, reading on instant claims 16 and 18.
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Further, Hu teaches the first and second exposure form features outside of regions 110A and 110B, such as features 500A and 800B (alignment marks) [0028, 0031, fig 8], where the scribe lines are located just outside of the regions 110A and 110B [fig 28, 0055], aligning with the instant first and second shot regions overlapping corresponding first and second scribe line regions, reading on instant claims 19-20.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 10 depends on claims 1 and 8, further disclosing that each of the second shot regions is overlapped with the first memory chip region in one of two adjacent interposer regions of the interposer regions and the second memory chip region in the other of the two adjacent interposer region.
A search did not find the claimed invention.
The closest prior art Hu et al. discloses a similar invention as shown above.
However, Hu only teaches an exposure region (shot region) overlapping different portions of an interposer die (interposer region), failing to teach simultaneously overlapping portions of two adjacent die.
Neither Hu nor the prior art in general provide sufficient motivation to make it obvious to modify their methods to arrive at the instantly claimed invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. “Large Area Interposer Lithography” teaches stitching used for interposer lithography. US20230324805A1 teaches a method for lithography stitching. US20220384325A1 teaches a method for fabricating an interposer die.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Lee whose telephone number is (571)272-2261. The examiner can normally be reached M-Th 7:30-5:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Keith Walker can be reached at (571) 272-3458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alexander N. Lee/Examiner, Art Unit 1737
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