DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/15/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner and made of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the
claimed invention and the prior art are such that the claimed invention as a whole would have
been obvious before the effective filing date of the claimed invention to a person having
ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
negated by the manner in which the invention was made.
Claims 1 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Lim, Sang Hoon (US 20210210565 A1) “Lim et al.” in view of PARK, Young Woo (US 20200371549 A1) “PARK et al.” further in view of BANG, Ki Ho (US 20200168685 A1) “BANG et al.”.
Regarding Independent Claim 1, Lim et al. Figs. 1-22 discloses a display device (“display panel 10” ¶ [0084]) comprising:
a substrate (“a flexible substrate” ¶ [0084]; “a substrate SUB” ¶ [0105]) comprising a main area (“a main region MR” ¶ [0085]) and a sub-area (“a protruding region BR/SR” ¶ [0085]) protruding from a side of the main area (“a protruding region BR/SR protruding from one side of the main region MR.” ¶ [0085]);
a circuit layer (“a thin-film transistor layer TFTL” ¶ [0105]) disposed on the substrate (“a thin-film transistor layer TFTL disposed on the substrate SUB” ¶ [0105]);
a light emitting element layer (“a light-emitting element layer EML” ¶ [0105]) disposed on the circuit layer (“a light-emitting element layer EML disposed on the TFTL” ¶ [0105]);
a sealing layer (“a thin-film encapsulation layer TFEL” ¶ [0105]) disposed on the light emitting element layer (“a thin-film encapsulation layer TFEL disposed on the EML” ¶ [0105]); and
a polarization layer (“a polarization layer PF” ¶ [0105]) disposed on the sealing layer and overlapping the light emitting element layer (Fig. 3 shows PF overlapping TFEL and EML),
wherein the main area comprises a display area (“a display area DA displaying images” ¶ [0088]) including a plurality of emission areas (“sub-pixels R, G and B” ¶ [00176]) and a non-display area (“non-display area NDA1” ¶ [0091]) disposed around the display area (“non-display area NDA1 surrounding the display area DA” ¶ [0091]),
the polarization layer extends to the non-display area and overlaps the buffer portion (Fig. 3 shows PF overlaps the NDA, therefore, PF overlaps buffer portion in NDA).
However, Lim et al. does not disclose the non-display area comprises:
a dam area spaced apart from the display area, the dam area including at least one dam portion that surrounds the display area; and
a bonding area surrounding the dam area,
the circuit layer comprises a buffer portion disposed in a part of the bonding area adjacent to the sub-area, the buffer portion being spaced apart from each of the sub-area and the dam area.
In the similar field of endeavor of display devices, PARK et al. Figs. 1-24 discloses the non-display area NDA (“non-display area NDA may surround an outer periphery of the display area DA” ¶ [0058]) comprises:
a dam area (“the display device may further include a dam at a boundary” ¶ [0022]) spaced apart from the display area (Fig. 5 shows DAM is spaced apart from DA), the dam area including at least one dam portion that surrounds the display area (“non-display area NDA may surround an outer periphery of the display area DA” ¶ [0058]); and
a bonding area (“The first additional area ADA1 may be connected to the non-display area NDA at a first boundary ED1.” ¶ [0059]) surrounding the dam area (Figs. 1-5 show NDA including DAM surrounding the DA),
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the non-display area of Lim et al. with the non-display area with the DAMs of PARK et al. in order to prevent the organic material of the second encapsulation film ENC2 of which fluidity is high from overflowing to the outside of the dam DAM during a process (e.g., formation process). The first and third encapsulation films ENC1 and ENC3 configured of the inorganic material may cover the dam DAM and extend, and thus adhesion to the substrate SUB or other films on the substrate SUB may be increased (PARK et al. ¶ [0137]).
However, PARK et al. does not disclose, the circuit layer comprises a buffer portion disposed in a part of the bonding area adjacent to the sub-area, the buffer portion being spaced apart from each of the sub-area and the dam area.
In the similar field of endeavor of display devices, BANG et al. Figs. 1-5 discloses the circuit layer comprises a buffer portion (“third dam DM3” ¶ [0058]) disposed in a part of the bonding area adjacent to the sub-area (“The bending part BDA” ¶ [0059]; “pad part PDA” ¶ [0060]), the buffer portion DM3 being spaced apart (Fig. 1 and Fig.5 show DM3 is spaced apart from BDA & PDA and DM1) from each of the sub-area BDA & PDA and the dam area (“first dam DM1” ¶ [0057]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the non-display area of Lim et al. as modified by PARK et al. including the buffer portion of BANG et el. in order to block an organic material of an encapsulation layer used for sealing the display part DA from flowing toward an edge portion of the substrate. The plurality of dams may prevent an edge tail of the organic material from being formed (BANG et al. ¶ [0053]).
Regarding Independent Claim 17, Lim et al. Figs. 1-22 discloses a display device (“display panel 10” ¶ [0084]) comprising:
a substrate (“a flexible substrate” ¶ [0084]; “a substrate SUB” ¶ [0105]) comprising a main area (“a main region MR” ¶ [0085]) and a sub-area (“a protruding region BR/SR” ¶ [0085]) protruding from a side of the main area (“a protruding region BR/SR protruding from one side of the main region MR.” ¶ [0085]);
a circuit layer (“a thin-film transistor layer TFTL” ¶ [0105]) disposed on the substrate (“a thin-film transistor layer TFTL disposed on the substrate SUB” ¶ [0105]);
a light emitting element layer (“a light-emitting element layer EML” ¶ [0105]) disposed on the circuit layer (“a light-emitting element layer EML disposed on the TFTL” ¶ [0105]);
a sealing layer (“a thin-film encapsulation layer TFEL” ¶ [0105]) disposed on the light emitting element layer (“a thin-film encapsulation layer TFEL disposed on the EML” ¶ [0105]);
a touch sensor layer (“The sensing layer TSL may be configured to sense a user's touch input and may perform the functions of a touch member” ¶ [0118]) disposed on the sealing layer (“A sensing unit TDU may have a sensing layer TSL that is disposed on the TFEL” ¶ [0105]); and
a polarization layer (“a polarization layer PF” ¶ [0105]) disposed on the sealing layer and overlapping the light emitting element layer (Fig. 3 shows PF overlapping TFEL and EML),
wherein the main area comprises a display area (“a display area DA displaying images” ¶ [0088]) including a plurality of emission areas (“sub-pixels R, G and B” ¶ [00176]) and a non-display area (“non-display area NDA1” ¶ [0091]) disposed around the display area (“non-display area NDA1 surrounding the display area DA” ¶ [0091]),
the polarization layer extends to the non-display area and overlaps the buffer portion (Fig. 3 shows PF overlaps the NDA, therefore, PF overlaps buffer portion in NDA).
However, Lim et al. does not disclose the non-display area comprises:
a dam area spaced apart from the display area, the dam area including at least one dam portion that surrounds the display area; and
a bonding area surrounding the dam area,
the circuit layer comprises a buffer portion disposed in a part of the bonding area adjacent to the sub-area, the buffer portion being spaced apart from each of the sub-area and the dam area.
the buffer portion comprises a compensation pattern layer and at least one compensation insulating layer covering the compensation pattern layer, and
In the similar field of endeavor of display devices, PARK et al. Figs. 1-24 discloses the non-display area NDA (“non-display area NDA may surround an outer periphery of the display area DA” ¶ [0058]) comprises:
a dam area (“the display device may further include a dam at a boundary” ¶ [0022]) spaced apart from the display area (Fig. 5 shows DAM is spaced apart from DA), the dam area including at least one dam portion that surrounds the display area (“non-display area NDA may surround an outer periphery of the display area DA” ¶ [0058]); and
a bonding area (“The first additional area ADA1 may be connected to the non-display area NDA at a first boundary ED1.” ¶ [0059]) surrounding the dam area (Figs. 1-5 show NDA including DAM surrounding the DA),
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the non-display area of Lim et al. with the non-display area with the DAMs of PARK et al. in order to prevent the organic material of the second encapsulation film ENC2 of which fluidity is high from overflowing to the outside of the dam DAM during a process (e.g., formation process). The first and third encapsulation films ENC1 and ENC3 configured of the inorganic material may cover the dam DAM and extend, and thus adhesion to the substrate SUB or other films on the substrate SUB may be increased (PARK et al. ¶ [0137]).
However, PARK et al. does not disclose, the circuit layer comprises a buffer portion disposed in a part of the bonding area adjacent to the sub-area, the buffer portion being spaced apart from each of the sub-area and the dam area, and the buffer portion comprises a compensation pattern layer and at least one compensation insulating layer covering the compensation pattern layer, and
In the similar field of endeavor of display devices, BANG et al. Figs. 1-5 discloses the circuit layer comprises a buffer portion (“third dam DM3” ¶ [0058]) disposed in a part of the bonding area adjacent to the sub-area (“The bending part BDA” ¶ [0059]; “pad part PDA” ¶ [0060]), the buffer portion DM3 being spaced apart (Fig. 1 and Fig.5 show DM3 is spaced apart from BDA & PDA and DM1) from each of the sub-area BDA & PDA and the dam area (“first dam DM1” ¶ [0057]) and the buffer portion DM3 comprises a compensation pattern layer (“pattern SM1” ¶ [0089]) and at least one compensation insulating layer covering (“insulating layer 121” ¶ [0089]) the compensation pattern layer SM1.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the non-display area of Lim et al. as modified by PARK et al. including the buffer portion of BANG et el. in order to block an organic material of an encapsulation layer used for sealing the display part DA from flowing toward an edge portion of the substrate. The plurality of dams may prevent an edge tail of the organic material from being formed (BANG et al. ¶ [0053]).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Lim, Sang Hoon (US 20210210565 A1) “Lim et al.” in view of PARK, Young Woo (US 20200371549 A1) “PARK et al.” further in view of BANG, Ki Ho (US 20200168685 A1) “BANG et al.” further in view of JEON; Yujin (US 20210265436 A1) “JEON et al.”.
Regarding Claim 2, Lim et al. as modified by PARK et al. and BANG et el. discloses the limitations of claim 1. Lim et al. Fig. 8 further discloses, wherein the circuit layer comprises:
a semiconductor layer (“a semiconductor layer ACT” ¶ [0181]) disposed on the substrate;
a first gate insulating layer disposed on the substrate and covering the semiconductor layer (“a first insulating layer ILL” ¶ [0181]);
a first conductive layer disposed on the first gate insulating layer (“a first conductive layer 110” ¶ [0181]);
a second gate insulating layer disposed on the first gate insulating layer and covering the first conductive layer (“a second insulating layer IL2” ¶ [0182]);
a second conductive layer disposed on the second gate insulating layer (“a second conductive layer 120” ¶ [0181]);
an interlayer insulating layer disposed on the second conductive layer and covering the second conductive layer (“a third insulating layer IL3” ¶ [0181]);
a third conductive layer disposed on the interlayer insulating layer (lower portion of 151 “layer 151” ¶ [0193]);
a first planarization layer disposed on the interlayer insulating layer and covering the third conductive layer (“fourth insulating layer IL4 may provide a flat surface over the level differences of the transistor” ¶ [0192]);
a fourth conductive layer disposed on the first planarization layer (Upper portion of 151 on IL4); and
a second planarization layer disposed on the first planarization layer and covering the fourth conductive layer (“film 140” ¶ [0193]),
However, Lim et al. does not disclose, wherein the at least one dam portion and the buffer portion are disposed on the interlayer insulating layer, and
the sealing layer contacts the interlayer insulating layer in portions of the bonding area external to the buffer portion.
In the similar field of endeavor of display devices, PARK et al. Figs. 1-24 discloses the at least one dam portion DAM and the buffer portion (DAM1 & DAM2 by OPN1 in Fig 5) are disposed on the interlayer insulating layer ILD.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the non-display area of Lim et al. with the non-display area with the DAMs of PARK et al. in order to prevent the organic material of the second encapsulation film ENC2 of which fluidity is high from overflowing to the outside of the dam DAM during a process (e.g., formation process). The first and third encapsulation films ENC1 and ENC3 configured of the inorganic material may cover the dam DAM and extend, and thus adhesion to the substrate SUB or other films on the substrate SUB may be increased (PARK et al. ¶ [0137]).
However, PARK et al. does not disclose, the sealing layer contacts the interlayer insulating layer in portions of the bonding area external to the buffer portion.
In the similar field of endeavor of display devices, JEON et al. Figs. 1-9 discloses, the sealing layer 410 (“encapsulation layer 410” ¶ [0124]) contacts the interlayer insulating layer 107 (“an interlayer insulating layer 107” ¶ [0096]) in portions of the bonding area external to the buffer portion 120 (“the second dam 120” ¶ [0141]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the non-display area of Lim et al. as modified by PARK et al. with the non-display area with the DAMs of JEON et al. in order to prevent from cracking due to a bending stress (JEON et al. ¶ [0174]).
Regarding Claim 3, Lim et al. as modified by PARK et al., BANG et el. And JEON et al. discloses the limitations of claim 2. However, Lim et al. does not disclose, wherein a width of the buffer portion in a first direction is equal to or greater than a width of the sub-area in a first direction, the first direction intersects a second direction, and the sub-area protrudes from the main area in the second direction.
In the similar field of endeavor of display devices, BANG et al. Figs. 1-4 discloses wherein a width of the buffer portion DM3 in a first direction D2 is equal to or greater than a width of the sub-area BDA & PDA in a first direction D2, the first direction D2 intersects a second direction D1, and the sub-area BDA & PDA protrudes from the main area DA in the second direction D1.
Allowable Subject Matter
Claim 4-16 and 18-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 4, Closest Prior arts of record Lim, Sang Hoon (US 20210210565 A1) “Lim et al.”, PARK, Young Woo (US 20200371549 A1) “PARK et al.”, BANG, Ki Ho (US 20200168685 A1) “BANG et al.” and JEON; Yujin (US 20210265436 A1) “JEON et al.”. alone or in combinations does not teach the third conductive layer comprises the compensation pattern layer, the first compensation insulating layer and the first planarization layer are a same layer, and the second compensation insulating layer and the second planarization layer are a same layer along with other limitations of claim 1.
Claims 5-16, indicated allowable based on their dependency on claim 4.
Regarding Claim 18, Closest Prior arts of record Lim, Sang Hoon (US 20210210565 A1) “Lim et al.”, PARK, Young Woo (US 20200371549 A1) “PARK et al.”, BANG, Ki Ho (US 20200168685 A1) “BANG et al.” and JEON; Yujin (US 20210265436 A1) “JEON et al.”. alone or in combinations does not teach a width of the compensation pattern layer in a first direction is equal to or greater than a width of the sub-area along with other limitations of claim 18.
Claims 19-25, indicated allowable based on their dependency on claim 18.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKHEE SARKER-NAG whose telephone number is (703)756-4655. The examiner can normally be reached Monday -Friday 7:15 AM to 5:30 PM.
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893