DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on November 15, 2023 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: COMPLEMENTARY FIELD-EFFECT TRANSISTOR (CFET) SEMICONDUCTOR STRUCTOR AND METHOD OF FORMING THE SAME.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Frougier (US 2023/0178544 A1) in view of Jo (US 2023/0352529 A1).
Claim 1, Frougier discloses a method for forming a semiconductor structure (a method of forming a CFET is disclosed and is a method for forming a semiconductor structure, hereinafter, method for forming a semiconductor structure, Fig. 21), comprising:
forming a bottom transistor (lower FET is a bottom transistor, hereinafter, bottom transistor, [0068], Fig. 4) over a substrate (bottom transistor is formed over substrate 110, [0068], Fig. 4), wherein the bottom transistor comprises a first nanostructure (nanosheet stack is formed of a first nanostructure (i.e. nanosheets within the lower FET device of the CFET) for the bottom transistor, [0070], Fig. 6), a first source/drain feature (lower FET source/drain regions 710 is a first source/drain feature, hereinafter, first source/drain feature 710, [0077], Fig. 7) adjoining the first nanostructure (first source/drain feature 710 is adjoining the first nanostructure, [0074], Fig. 7) and a first work function layer (bottom device WFM 2710 is a first work function layer, hereinafter, first work function layer 2710, [0098], Fig. 27) wrapping the first nanostructure (first work function layer 2710 is wrapping around the first nanostructure, [0098], Fig. 27); and
forming a top transistor (upper FET is a top transistor, hereinafter, top transistor, [0087], Fig. 4) above the bottom transistor (top transistor is formed above the bottom transistor, [0088], Fig. 17), wherein the top transistor comprises a second nanostructure (nanosheet stack is formed of a second nanostructure (i.e. nanosheets within the upper FET device of the CFET) for the top transistor, [0070], Fig. 6), a second source/drain feature (upper FET source/drain regions 730 is a second source/drain feature, hereinafter, second source/drain feature 730, [0077], Fig. 7) adjoining the second nanostructure (second source/drain feature 730 is adjoining the second nanostructure, [0074], Fig. 7) and a second work function layer (work-function metal (WFM) layers 1620 are second work function layers, hereinafter, second work function layer 1620, [0086], Fig. 16) wrapping the second nanostructure (second work function layer 1620 is wrapping the second nanostructure, [0086], Fig. 16),
wherein the first source/drain feature 710 is physically isolated from the second source/drain feature 730 (first source/drain feature 710 is physically isolated from the second source/drain feature 730 by dielectric spacer layer 720, [0076], Fig. 7).
Frougier does not explicitly disclose a first thickness of the first nanostructure is different than a second thickness of the second nanostructure.
However, Jo discloses a first thickness of the first nanostructure (Jo, lower nanosheet transistor 10L includes the lower channel structure 110 is a first nanostructure, hereinafter, first nanostructure 110 with a first thickness, hereinafter, first thickness TH1, [0071], Fig. 1C; Frougier, first nanostructure, Fig. 2) is different than a second thickness of the second nanostructure (Jo, upper-stack nanosheet transistor 10U includes the upper channel structure 120 is a second nanostructure, hereinafter, second nanostructure 120 with a second thickness, hereinafter, second thickness TH2, [0071], Fig. 1C; Frougier, first nanostructure, Fig. 2). The combination to manipulate the channel thickness between the lower and upper FETs within the CFET device allows for CMOS implementation as well as desired manipulation of the separate upper and lower work-function metal layer processing steps (Jo, [0007]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to manipulate the channel thickness between the lower and upper FETs within the CFET device allows for CMOS implementation as well as desired manipulation of the separate upper and lower work-function metal layer processing steps (Jo, [0007]).
Claim 2, Frougier/Jo discloses the method for forming the semiconductor structure (Jo, Figs. 1A-1D; Frougier, Fig. 21) as claimed in claim 1.
Frougier/Jo discloses wherein the first source/drain feature (Jo, first source/drain feature, hereinafter, first source/drain feature 112, [0070], Figs. 1A-1D; Frougier, first source/drain feature 710, [0077], Fig. 7) is doped with a p-type dopant (Jo, first source/drain feature 112 is doped with a p-type dopant, [0038], Figs. 1A-1D; Frougier, first source/drain feature 710 is doped with a p-type dopant, [0075], Fig. 7), and the second source/drain feature (Jo, upper source/drain regions 122 is a second source/drain feature, hereinafter, second source/drain feature 122, [0038], Figs. 1A-1D; Frougier, second source/drain feature 730, [0077], Fig. 7) is doped with an n-type dopant (Jo, second source/drain feature 122 is doped with an n-type dopant, [0038], Figs. 1A-1D; Frougier, second source/drain feature 730 is doped with an n-type dopant, [0075], Fig. 7).
Claim 3, Frougier/Jo discloses the method for forming the semiconductor structure (Jo, Figs. 1A-1D; Frougier, Fig. 21) as claimed in claim 1, further comprising:
forming a first active region (Jo, lower channel structure 110 is a first active region, hereinafter, first active region 110, [0039], Figs. 1A-1D; Frougier, bottom nanosheet channels 130 form a first active region, hereinafter, first active region 130, [0074], Fig. 7) over the substrate (Jo, first active region 110 is formed over substrate 105, [0037], Figs. 1A-1D; Frougier, first active region 130 is formed over the substrate 110, [0060], Fig. 21);
patterning the first active region to form the first nanostructure (Jo, first active region 110 is patterned to form the first nanostructure 110, [0037], Figs. 1A-1D; Frougier, first active region 130 is patterned to form the first nanostructure, [0060], Fig. 21);
forming the first work function layer to wrap the first nanostructure (Jo, lower work-function metal layer 115F is formed to wrap the first nanostructure and is a first work function layer, hereinafter, first work function layer 115F, [0044], Figs. 1A-1D; Frougier, first work function layer 2710 is formed to wrap around the first nanostructure, [0098], Fig. 27);
bonding a bonding dielectric material (Jo, gate dielectric layer 115D is a bonding dielectric material, hereinafter, bonding dielectric material 115D, [0044], Figs. 1A-1D; Frougier, insulating layer 120 is a bonding dielectric material, hereinafter, bonding dielectric material 120, [0060], Fig. 27) over the first work function layer (Jo, bonding dielectric material 115D is bonded over the first work function layer 115F, Figs. 1A-1D; Frougier, bonding dielectric material 120 is formed over the first work function layer 2710, [0098] Fig. 30);
forming a second active region (Jo, upper channel structure 120 is a second active region, hereinafter, second active region 120, [0039], Figs. 1A-1D; Frougier, upper nanosheet channels 130 form a second active region, hereinafter, second active region 130, [0074], Fig. 7) over the bonding dielectric material (Jo, second active region 120 is formed over the bonding dielectric material 115D, [0044], Figs. 1A-1D; Frougier, second active region 130 is formed over the bonding dielectric material 120, [0060], Fig. 21);
patterning the second active region to form the second nanostructure (Jo, second active region 120 is patterned to form the second nanostructure 120, [0037], Figs. 1A-1D; Frougier, second active region 130 is patterned to form the second nanostructure, [0060], Fig. 21); and
forming the second work function layer to wrap the second nanostructure (Jo, upper work-function metal layer 125F is formed to wrap the second nanostructure and is a second work function layer, hereinafter, second work function layer 115F, [0044], Figs. 1A-1D; Frougier, second work function layer 1620 is formed to wrap the second nanostructure, [0086], Fig. 16).
Claim 4, Frougier/Jo discloses the method for forming the semiconductor structure (Jo, Figs. 1A-1D; Frougier, Fig. 21) as claimed in claim 3.
Frougier/Jo discloses wherein a first width of the first fin structure is different than a second width of the second fin structure (Jo, lower channel structure 110 is a first fin structure with a first width that is different than that of the upper channel structure 120 which is a second fin structure with a second with, [0034], Figs. 1A-1D; Frougier, width of any nanosheet layer can be varied, [0058], Fig. 1).
Claim 5, Frougier/Jo discloses the method for forming the semiconductor structure (Jo, Figs. 1A-1D; Frougier, Fig. 21) as claimed in claim 1.
Frougier/Jo discloses wherein the first work function layer (Jo, first work function layer 115F, [0044], Figs. 1A-1D; Frougier, first work function layer 2710, [0098], Fig. 27) and the second work function layer (Jo, second work function layer 115F, [0044], Figs. 1A-1D; Frougier, second work function layer 1620, [0086], Fig. 16) are made of different materials (Jo, first work function layer 115F and second work function layer 125F are made of different materials, [0082], Figs. 1A-1D; Frougier, first work function layer 2710 and second work function layer 1620 are made of different materials, [0098], Figs. 16, 27, and 30).
Claim 6, Frougier discloses a method for forming a semiconductor structure (a method of forming a CFET is disclosed and is a method for forming a semiconductor structure, hereinafter, method for forming a semiconductor structure, Fig. 21), comprising:
forming a stack in which lower sacrificial layers (sacrificial semiconductor material layers 140 are lower sacrificial layers, hereinafter, lower sacrificial layers 140, [0061], Fig. 1B) and lower channel layers (semiconductor channel material layers 130 are lower channel layers, hereinafter, lower channel layers 130, [0061], Fig. 1B) are alternatingly stacked in a bottom device region of the stack (lower FET is a stack in which lower sacrificial layers 140 and lower channel layers 130 are alternatingly stacked in a bottom device region of the stack, [0068], Fig. 4), and upper sacrificial layers (sacrificial semiconductor material layers 140 are upper sacrificial layers, hereinafter, upper sacrificial layers 140, [0061], Fig. 1B) and upper channel layers (semiconductor channel material layers 130 are upper channel layers, hereinafter, upper channel layers 130, [0061], Fig. 1B) are alternatingly stacked in a top device region of the stack over the bottom device region (upper FET is a stack in which lower sacrificial layers 140 and lower channel layers 130 are alternatingly stacked in a top device region of the stack over the bottom device region, [0068], Fig. 4);
patterning the stack to form a fin structure (lower channel layers 130 and upper channel layers 130 is patterned to form a fin structure, [0060], Fig. 21);
removing the lower sacrificial layers and the upper sacrificial layers to expose the lower channel layers and the upper channel layers (removing the lower sacrificial layers 140 and the upper sacrificial layers 140 to expose the lower channel layers 130 and the upper channel layers 130, [0079], Fig. 9); and
forming a gate stack surrounding the lower channel layers and the upper channel layers (forming a gate stack 1610 surrounding the lower channel layers 130 and the upper channel layers 130, [0087], Fig. 16).
Frougier does not explicitly disclose wherein a first thickness of the lower channel layers is different than a second thickness of the upper channel layers.
However, Jo discloses a first thickness of the lower channel layers (Jo, lower nanosheet transistor 10L includes the lower channel structure 110 with a first thickness, hereinafter, first thickness TH1, [0071], Fig. 1C; Frougier, first nanostructure, Fig. 2) is different than a second thickness of the upper channel layers (Jo, upper-stack nanosheet transistor 10U includes the upper channel structure 120 with a second thickness, hereinafter, second thickness TH2, [0071], Fig. 1C; Frougier, first nanostructure, Fig. 2). The combination to manipulate the channel thickness between the lower and upper FETs within the CFET device allows for CMOS implementation as well as desired manipulation of the separate upper and lower work-function metal layer processing steps (Jo, [0007]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to manipulate the channel thickness between the lower and upper FETs within the CFET device allows for CMOS implementation as well as desired manipulation of the separate upper and lower work-function metal layer processing steps (Jo, [0007]).
Claim 7, Frougier/Jo discloses the method for forming the semiconductor structure (Jo, Figs. 1A-1D; Frougier, Fig. 21) as claimed in claim 6, further comprising:
recessing the fin structure to form a source/drain recess (Frougier, recessing the fin structure (i.e. nanosheet stack layers 130/140) to form a source/drain recess, [0070], Fig. 6; Jo, Figs. 1A-1D);
forming a bottom source/drain feature (Frougier, lower FET source/drain regions 710 is a bottom source/drain feature, hereinafter, bottom source/drain feature 710, [0077], Fig. 7; Jo, first source/drain feature, hereinafter, bottom source/drain feature 112, [0070], Figs. 1A-1D) adjoining the lower channel layers in the source/drain recess (Frougier, bottom source/drain feature 710 is adjoining the lower channel layers 130 in the source/drain recess, [0074], Fig. 7; Jo, bottom source/drain feature 112 is adjoining the lower channel layers 110 in the source/drain recess, [0070], Figs. 1A-1D);
forming a lower interlayer dielectric layer (Frougier, dielectric spacer layer 720 is a lower interlayer dielectric layer, hereinafter, lower interlayer dielectric layer 720, [0076], Fig. 7; Jo, interlayer dielectric (ILD) structure 160 is a lower interlayer dielectric layer, hereinafter, lower interlayer dielectric layer 160, [0039], Figs. 1A-1D) to cover the lower source/drain feature (Frougier, lower interlayer dielectric layer 720 is formed to cover the lower source/drain regions 710, [0076], Fig. 7; Jo, lower interlayer dielectric layer 160 is formed to cover the lower source/drain regions 112, [0039], Figs. 1A-1D); and
forming a top source/drain feature (Jo, upper source/drain regions 122 is a top source/drain feature, hereinafter, top source/drain feature 122, [0038], Figs. 1A-1D; Frougier, top source/drain feature 730, [0077], Fig. 7) adjoining the upper channel layers in the source/drain recess (Jo, top source/drain feature 122 adjoins the upper channel layers 120 in the source/drain recess, [0038], Figs. 1A-1D; Frougier, top source/drain feature 730 adjoins the upper channel layers 130 in the source/drain recess, [0077], Fig. 7), wherein the top source/drain feature has a different conductivity type than the bottom source/drain feature (Jo, first source/drain feature 112 is doped with a p-type dopant while the second source/drain feature 122 is doped with an n-type dopant, [0038], Figs. 1A-1D; Frougier, first source/drain feature 710 is doped with a p-type dopant while the second source/drain feature 730 is doped with an n-type dopant, [0075], Fig. 7).
Claim 8, Frougier/Jo discloses the method for forming the semiconductor structure (Jo, Figs. 1A-1D; Frougier, Fig. 21) as claimed in claim 7, further comprising:
forming a first contact plug (Frougier, S/D region contacts 2020 are a first contact plug, hereinafter, first contact plug 2020, [0091], Figs. 20 and 30; Jo, top source/drain feature 122, [0038], Figs. 1A-1D) on a top surface of the top source/drain feature (Frougier, first contact plug 2020 is formed on a top surface of the top source/drain feature 730, [0091], Figs. 20 and 30; Jo, top source/drain feature 122, [0038], Figs. 1A-1D); and
forming a second contact plug (Frougier, middle-of-line S/D contacts 2910 are a second contact plug, hereinafter, second contact plug 2910, [0100], Fig. 30; Jo, Figs. 1A-1D) on a bottom surface of the bottom source/drain feature (Frougier, second contact plug 2910 is formed on a bottom surface of the bottom source/drain feature 710, [0077], Fig. 30; Jo, bottom source/drain feature 112, [0070], Figs. 1A-1D).
Claim 9, Frougier/Jo discloses the method for forming the semiconductor structure (Jo, Figs. 1A-1D; Frougier, Fig. 21) as claimed in claim 6.
Frougier/Jo discloses wherein a first height of the bottom source/drain feature (Frougier, bottom source/drain feature 710, [0077], Fig. 30; Jo, bottom source/drain feature 112, [0070], Figs. 1A-1D) is different than a second height of the top source/drain feature (Frougier, top source/drain feature 730, [0091], Figs. 20 and 30; Jo, top source/drain feature 122, [0038], Figs. 1A-1D).
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Annotated Fig. 30 (Frougier) – Illustrates wherein a first height of the bottom source/drain feature 710 is different than a second height of the top source/drain feature 730
Claim 10, Frougier/Jo discloses the method for forming the semiconductor structure (Jo, Figs. 1A-1D; Frougier, Fig. 21) as claimed in claim 6.
Frougier/Jo discloses wherein there is a different number of lower channel layers than upper channel layers (Jo, there is a different number of lower channel layers 110C than upper channel layers 120C (i.e. two lower channel layers 110C vs. three upper channel layers 120C), [0035], Figs. 1A-1D; Frougier, any number and combinations of layers can be used to form lower and upper devices, [0058], Fig. 30).
Claim 11, Frougier/Jo discloses the method for forming the semiconductor structure (Jo, Figs. 1A-1D; Frougier, Fig. 21) as claimed in claim 6, wherein forming the gate stack comprises:
forming a bottom work function layer (Jo, initial work-function metal layer 115F’ is a bottom work function layer, hereinafter, bottom work function layer 115F/115F’, [0080], Fig. 4; Frougier, bottom work function layer 2710, [0098], Figs. 27 and 30) surrounding the lower channel layers and the upper channel layers (Jo, bottom work function layer 115F/115F’ is formed to surround the lower channel layers 110C and the upper channel layers 120C, [0080], Fig. 4; Frougier, bottom work function layer 2710 surrounds lower channel layers 130, [0098], Figs. 27 and 30); and
forming a top work function layer (Jo, upper work-function metal layer 125F is formed to wrap the second nanostructure and is a second work function layer, hereinafter, second work function layer 115F, [0044], Figs. 1A-1D; Frougier, work-function metal (WFM) layers 1620 are top work function layers, hereinafter, top work function layer 1620, [0086], Fig. 16) surrounding the upper channel layers (Jo, second work function layer 115F surround the upper channel layers 120, [0044], Figs. 1A-1D; Frougier, top work function layer 1620 surround the upper channel layers 130, [0086], Fig. 16), wherein the bottom work function layer is made of a different material than the top work function layer (Jo, bottom work function layer 115F/115F’ and second work function layer 125F are made of different materials, [0082], Figs. 1A-1D; Frougier, first work function layer 2710 and second work function layer 1620 are made of different materials, [0098], Figs. 16, 27, and 30).
Claim 12, Frougier/Jo discloses the method for forming the semiconductor structure (Jo, Figs. 1A-1D; Frougier, Fig. 21) as claimed in claim 11.
Frougier/Jo discloses further comprising:
forming an isolation layer (Jo, gate dielectric layer 115D is an isolation layer, hereinafter, isolation layer 115D, [0044], Figs. 1A-1D; Frougier, insulating layer 120 is an isolation layer, hereinafter, isolation layer 120, [0060], Fig. 27) between the bottom work function layer and the top work function layer (Jo, isolation layer 115D is formed vertically between the bottom work function layer 115F/115F’ and the top work function layer 125F, [0044], Figs. 1A-1D; Frougier, isolation layer 120 is formed between the bottom work function layer 2710 and the top work function layer 1620, [0060], Fig. 27).
Claim 15, Frougier discloses a semiconductor structure (semiconductor structure, Fig. 30), comprising:
a bottom transistor (lower FET is a bottom transistor, hereinafter, bottom transistor, [0068], Fig. 4) comprising a plurality of first nanostructures (nanosheet stack includes a plurality of first nanostructure (i.e. nanosheets within the lower FET device of the CFET) for the bottom transistor, [0070], Fig. 6), a first source/drain feature (lower FET source/drain regions 710 is a first source/drain feature, hereinafter, first source/drain feature 710, [0077], Fig. 7) adjoining the plurality of first nanostructures (first source/drain feature 710 is adjoining the plurality of first nanostructures, [0074], Fig. 7) and a first gate stack wrapping the plurality of first nanostructures (first gate stack includes bottom device WFM 2710, hereinafter, first gate stack 2710, [0098], Fig. 27);
a top transistor (upper FET is a top transistor, hereinafter, top transistor, [0087], Fig. 4) above the bottom transistor (top transistor is formed above the bottom transistor, [0088], Fig. 17), comprising a plurality of second nanostructures (nanosheet stack is formed of a plurality of second nanostructures (i.e. nanosheets within the upper FET device of the CFET) for the top transistor, [0070], Fig. 6), a second source/drain feature (upper FET source/drain regions 730 is a second source/drain feature, hereinafter, second source/drain feature 730, [0077], Fig. 7) adjoining the plurality of second nanostructures (second source/drain feature 730 is adjoining the plurality of second nanostructure, [0074], Fig. 7) and a second gate stack (second gate stack includes work-function metal (WFM) layers 1620 and is a second gate stack 1620, [0086], Fig. 16) wrapping the plurality of second nanostructures (second gate stack 1620 is wrapping the plurality of second nanostructures, [0086], Fig. 16); and
an interlayer dielectric layer (dielectric spacer layer 720 is an interlayer dielectric layer, hereinafter, interlayer dielectric layer 720, [0076], Fig. 7) interposing between the first source/drain feature 710 and the second source/drain feature 730 (interlayer dielectric layer 720 is interposing between the first source/drain feature 710 and the second source/drain feature 730 by, [0076], Fig. 7).
Frougier does not explicitly disclose a first thickness of the first nanostructure is different than a second thickness of the second nanostructure.
However, Jo discloses a first thickness of the first nanostructure (Jo, lower nanosheet transistor 10L includes the lower channel structure 110 is a first nanostructure, hereinafter, first nanostructure 110 with a first thickness, hereinafter, first thickness TH1, [0071], Fig. 1C; Frougier, first nanostructure, Fig. 2) is different than a second thickness of the second nanostructure (Jo, upper-stack nanosheet transistor 10U includes the upper channel structure 120 is a second nanostructure, hereinafter, second nanostructure 120 with a second thickness, hereinafter, second thickness TH2, [0071], Fig. 1C; Frougier, first nanostructure, Fig. 2). The combination to manipulate the channel thickness between the lower and upper FETs within the CFET device allows for CMOS implementation as well as desired manipulation of the separate upper and lower work-function metal layer processing steps (Jo, [0007]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to manipulate the channel thickness between the lower and upper FETs within the CFET device allows for CMOS implementation as well as desired manipulation of the separate upper and lower work-function metal layer processing steps (Jo, [0007]).
Claim 16, Frougier/Jo discloses the semiconductor structure (Jo, Figs. 1A-1D; Frougier, Fig. 21) as claimed in claim 15.
Frougier/Jo discloses wherein the plurality of second nanostructures overlaps the plurality of first nanostructures (Frougier, the plurality of second nanostructures overlaps the plurality of first nanostructures, Fig. 30; Jo, the plurality of second nanostructures overlaps the plurality of first nanostructures, Figs. 1A-1D), and the second source/drain feature overlaps the first source/drain feature (Frougier, the second source/drain feature overlaps the first source/drain feature, Fig. 30; Jo, the second source/drain feature overlaps the first source/drain feature, Figs. 1A-1D).
Claim 17, Frougier/Jo discloses the semiconductor structure (Jo, Figs. 1A-1D; Frougier, Fig. 21) as claimed in claim 15.
Frougier/Jo discloses wherein the first gate stack includes a p-type work function layer (Jo, first gate stack includes a p-type work function layer when the first source/drain feature 710 is p-type, [0038], Figs. 1A-1D; Frougier, first gate stack includes a p-type work function layer when the first source/drain feature 112 is p-type, [0075], Fig. 7), and the second gate stack includes an n-type work function layer (Jo, second gate stack includes an n-type work function layer when the second source/drain feature 730 is n-type, [0038], Figs. 1A-1D; Frougier, second gate stack includes an n-type work function layer when the second source/drain feature 122 is n-type, [0075], Fig. 7).
Claim 18, Frougier/Jo discloses the semiconductor structure (Jo, Figs. 1A-1D; Frougier, Fig. 21) as claimed in claim 15.
Frougier/Jo discloses wherein there is a different number of first nanostructures than second nanostructures (Jo, there is a different number of first nanostructures 110C than second nanostructures 120C (i.e. two first nanostructures 110C vs. three second nanostructures 120C), [0035], Figs. 1A-1D; Frougier, any number and combinations of layers can be used to form lower and upper devices, [0058], Fig. 30).
Claim 19, Frougier/Jo discloses the semiconductor structure (Jo, Figs. 1A-1D; Frougier, Fig. 21) as claimed in claim 15.
Frougier/Jo discloses wherein a first width of the first nanostructures is different than a second width of the second nanostructures (Jo, first width of first nanostructures 110C is different than the second width of the second nanostructures 120C, [0034], Figs. 1A-1D; Frougier, width of any nanosheet layer can be varied, [0058], Fig. 1).
Claim 20, Frougier/Jo discloses the semiconductor structure (Jo, Figs. 1A-1D; Frougier, Fig. 21) as claimed in claim 15.
Frougier/Jo discloses wherein the first source/drain feature (Jo, first source/drain feature 112, [0070], Figs. 1A-1D; Frougier, first source/drain feature 710, [0077], Fig. 7) is electrically connected to a power rail (Jo, first source/drain feature 112 is electrically connected to a power rail, [0070], Figs. 1A-1D; Frougier, first source/drain feature 710 is electrically connected to a power rail, [0077], Fig. 7), and the second source/drain feature (Jo, second source/drain feature 122, [0038], Figs. 1A-1D; Frougier, second source/drain feature 730, [0077], Fig. 7) is electrically connected to a power rail (Jo, second source/drain feature 122 is electrically connected to a power rail, [0038], Figs. 1A-1D; Frougier, second source/drain feature 730 is electrically connected to a power rail, [0077], Fig. 7).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Frougier in view of Jo and further in view of Huang (US 2023/0178552 A1).
Claim 13, Frougier/Jo discloses the method for forming the semiconductor structure (Jo, Figs. 1A-1D; Frougier, Fig. 21) as claimed in claim 6.
Frougier/Jo does not explicitly disclose wherein the lower channel layers are made of a different material than the upper channel layers.
However, Huang discloses wherein the lower channel layers (Huang, nanoribbons 104 are lower channel layers, hereinafter, lower channel layers 104, [0032], Figs. 1A-1C; Jo, lower channel layers 110C, [0034], Figs. 1A-1D; Frougier, lower channel layers 130, [0058], Fig. 1) are made of a different material than the upper channel layers (Huang, nanoribbons 106 are upper channel layers, hereinafter, upper channel layers 106 and may be made of a different material than the lower channel layers 104, [0032], Figs. 1A-1C; Jo, lower channel layers 110C and upper channel layers 120C, [0034], Figs. 1A-1D; Frougier, lower channel layers 130 and upper channel layers 130, [0058], Fig. 1). The combination to utilize different materials as channel material for the NFET and PFET allow for optimizing the material configuration of the CFET device (Huang, [0031]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize different materials as channel material for the NFET and PFET allow for optimizing the material configuration of the CFET device (Huang, [0031]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Frougier in view of Jo and further in view of Xie (US 2023/0125316 A1).
Claim 14, Frougier/Jo discloses the method for forming the semiconductor structure (Jo, Figs. 1A-1D; Frougier, Fig. 21) as claimed in claim 6.
Frougier/Jo does not explicitly disclose wherein each of the upper channel layers is thicker than each of the lower channel layers.
However, Xie discloses wherein each of the upper channel layers (Xie, semiconductor channel material layers 16 within second nanosheet material stack MS2, hereinafter, upper channel layers 16/MS2, [0038], Figs. 2A-2B; Jo, upper-stack nanosheet transistor 10U includes the upper channel structure 120 are upper channel layers, hereinafter, upper channel layers 120 with a second thickness, hereinafter, second thickness TH2, [0071], Fig. 1C; Frougier, first nanostructure, Fig. 2) is thicker than each of the lower channel layers (Xie, thickness of upper channel layers 16/MS2 is different than the semiconductor channel material layers 16 within first nanosheet material stack MS1, hereinafter, lower channel layers 16/MS1, [0038], Figs. 2A-2B Jo, lower nanosheet transistor 10L includes the lower channel structure 110 are lower channel layers, hereinafter, lower channel layers 110 with a first thickness, hereinafter, first thickness TH1, [0071], Fig. 1C; Frougier, first nanostructure, Fig. 2). The combination to modify the channel layer thickness between NFET and PFET within the CFET would allow for further optimization of the opposite polarity of adjacent stacks (Xie, [0039]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the channel layer thickness between NFET and PFET within the CFET would allow for further optimization of the opposite polarity of adjacent stacks (Xie, [0039]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEVY J BOEGEL whose telephone number is (703)756-1299. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812