DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: claims 11-12 recites of “a first region,” “a second region,” “a first portion of the first region,” “a second portion of the first region,” “a second portion of the first region,” and “a second portion of the second region.” For the purpose of compact prosecution, the examiner will refer to corresponding regions and portions as labelled in the annotated Figure 1 below of the instant application.
PNG
media_image1.png
362
907
media_image1.png
Greyscale
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9 and 10 are rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by Cheng ‘046 (US 2018/0083046 A1).
Regarding claim 9, Cheng ‘046 teaches a method comprising:
providing a nanosheet (layers 122, 106, 120, 104, 118, 102, 116 and 130, 112, 128, 110, 126, 108, 124 as shown in Fig. 1);
forming (see method Figs. 2-10) a transistor component (left side of Fig. 15, with the left and right sides separated by 700 along the vertical axis; see FET in ¶ [0052]) utilizing a first portion (left side of Fig. 15, with the left and right sides separated by 700 along the vertical axis) of the nanosheet; and
forming (see method Fig. 11) a capacitor component (right side of Fig. 15 and ¶ [0050] ) utilizing a second portion (right side nanosheet in Fig. 1; see ¶ [0036] ) of the nanosheet.
Regarding claim 10, the method of claim 9, wherein forming the capacitor comprises: masking the transistor (using mask 1100, see Fig. 11), doping the second portion of the nanosheet to render it more conductive than the first portion of the nanosheet (see ¶ [0049]-[0050]: adding dopants to semiconductor materials are known in the art to make the material more conductive; also ¶ [0052]: doped regions 504/506 become a second terminal), depositing a dielectric (1306, see Fig. 13), and depositing a conductive material (1302) separated from the second portion of the nanosheet by the dielectric (Fig. 13 shows 1302 separated from 504/506/108/108/110/112 by 1306).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng ‘144 (US 2022/0302144 A1) in view of Cheng ‘046 (US 2018/0083046 A1).
Regarding claim 1, Cheng ‘144 teaches a memory element (1800, see Fig. 18; ¶ [0091]: 1T1C FeRAM ) comprising:
a transistor (1820 in device region 2, see ¶ [0092] ) including a channel (1821), a source region (1827; see ¶ [0090] ), a drain region (1825) and a gate component (1823) on at least one side (top side of 1821) of the channel between the source region and drain region (Fig. 19 shows 1823 between 1825 and 1827), the channel provided in a first portion (200) of a nanosheet (200&100; see method drawings Figs 1-7; ¶ [0056]: stacked layers of 122 is a nanosheet); and
a capacitor (1810 in device region 1; see Fig. 18 and ¶ [0089] ) having a first capacitor component (1811&1815) and second capacitor component (1813) separated by an insulator (1812; see ¶ [0087] ), the first capacitor component provided in a second portion (100; see method drawings Figs 1-7) of the nanosheet.
Cheng ‘144 further teaches the first capacitor component to be an electrode of the capacitor (¶ [0087] ). However, Cheng ‘144 does not teach: the first capacitor component provided in a second portion of the nanosheet.
Cheng ‘046, in the same field of invention, teaches a first capacitor component (504 & 506 & 108 & 110 & 112 ; see Fig. 15 and ¶ [0052]: “doped regions 504 and 506 act as a second terminal”; note: a terminal is also known in the art to be an electrode; right side of Fig. 15 is a capacitor, see ¶ [0050] ) provided in a second portion (right side nanosheet in Fig. 1; see ¶ [0036]) of the nanosheet (nanosheet comprises of layers 122, 106, 120, 104, 118, 102, 116 and 130, 112, 128, 110, 126, 108, 124 as shown in Fig. 1; Fig. 15 shows nanosheet layers 108, 110, and 112 are part of 504 & 506).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Cheng ‘046 into the device of Cheng ‘144 to provide the first capacitor component in a second portion of the nanosheet. The ordinary artisan would have been motivated to modify Cheng ‘144 in the manner set forth above for at least the purpose of creating a nanosheet capacitor (Cheng ¶ [0006] ) for the further purpose of reducing short-channel effects, reducing leakage and parasitic capacitances, and improving the device performance (Cheng ‘046 ¶ [0003] ).
Regarding claim 4, the memory element of claim 1, wherein the first portion of the nanosheet has a different doping characteristic than the second portion of the nanosheet (Cheng ‘046 Fig. 11 and ¶ [0049]-[0050] explains the capacitor side of the nanosheet are doped with n-type or p-type dopants while the transistor side is covered by mask 1100 to prevent being doped; hence Cheng ‘046 teaches “a different doping characteristic” between the first portion and the second portion of the nanosheet).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng ‘144 (US 2022/0302144 A1) in view of Cheng ‘046 (US 2018/0083046 A1) as applied to claim 1 above, and in further view of Sharma (US 2024/0008291 A1).
Regarding claim 2, Cheng ‘144 et al. teach the memory element of claim 1, but do not teach the device wherein the second capacitor component extends to another memory element.
Sharma, in the same field of invention, teaches a memory device (¶ [0022] ) with a first memory element (top row of nanosheet 116; see Figs. 1B, 1C, 2A, and 2C) and another memory element (second row of 116 from the top), wherein the second capacitor component (plate 135 of the capacitor 133 of the top row) extends to another memory element (bottom capacitor 133 of the second row from the top; above-mentioned Figures show the 135 of the top row contacting and/or vertically extending towards the dielectric layer 134 of the capacitor 133 of the second row from the top; see also ¶ [0035]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Sharma into the device of Cheng ‘144 et al. to have the second capacitor component extend to another memory device element. The ordinary artisan would have been motivated to modify Cheng ‘144 et al. in the manner set forth above for at least the purpose of increasing the device density and reducing manufacturing cost of a memory device (101) comprising of an array of the memory element (Sharma ¶ [0001], ¶ [0022]-[0024], ¶ [0027] ).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng ‘144 (US 2022/0302144 A1) in view of Cheng ‘046 (US 2018/0083046 A1) as applied to claim 1 above, and further in view of Na (US 2022/0238634 A1).
Regarding claim 3, Cheng ‘144 et al. teach the memory element of claim 1, but do not teach the device wherein the second capacitor component is coupled to ground.
Na, in the same field of invention, teaches a memory element (20, see Fig. 7 or MC in Figs. 10-1; also see ¶ [0130], ¶ [0132] ) wherein the second capacitor component (CE) is coupled to ground (Vdd; Figs. 10-11 shows the lower terminal of the capacitor is connected to the ground).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Na into the device of Cheng ‘144 et al. to connect the second capacitor component to ground. The ordinary artisan would have been motivated to modify Cheng ‘144 et al. in the manner set forth above for at least the purpose of using the memory element as part of a larger array of memory elements (930 in Na Fig. 10; or 3010 in Fig. 11) wherein the transistor and capacitors are connected to a bit line (BL) for memory read / write operations (Na ¶ [0130], ¶ [0132] ). The ordinary artisan would note that it is common knowledge in the art to use the capacitor as a storage mechanism to store charges during read / write operations and hence needs to be connected to a ground potential to set a potential basis of the charges stored.
Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng ‘046 (US 2018/0083046 A1) and in view of Sharma (US 2024/0008291 A1).
Regarding claim 5, Cheng ‘046 teaches a device comprising:
a transistor (left side of Fig. 15, with the left and right sides separated by 700 along the vertical axis) provided in a first portion (left side of nanosheet in Fig. 1; see ¶ [0036]) of a first nanosheet (layers 122, 106, 120, 104, 118, 102, 116 and 130, 112, 128, 110, 126, 108, 124 as shown in Fig. 1) and a capacitor component (right side of Fig. 15; see ¶ [0050]) provided in a second portion (right side nanosheet in Fig. 1; see ¶ [0036] ) of the first nanosheet.
Cheng ‘046 further teaches the transistor and capacitor to be serially connected to each other along an axis (horizonal axis of Fig. 15).
However, Cheng ‘046 does not teach the transistor and capacitor to be part of a first memory element; and
a second memory element including a transistor provided in a first portion of a second nanosheet and a capacitor component provided in a second portion of the second nanosheet.
Sharma, in the same field of invention, teaches a memory device (¶ [0022] ) comprising of a first memory element (top row of structure in Figs. 1 and 2) that is further comprised of a transistor (122 of top row) and at least one capacitor (133 of the top row) connected serially to each other along an axis (x-axis; see also ¶ [0030] ); and
a second memory element (second row from the top) including a transistor (122 of second row) provided in a first portion (portion of 116 of the second row under 122) of a second nanosheet (116 of the second row) and a capacitor (133 of the second row) component provided in a second portion (portion of 116 of the second row under 133) of the second nanosheet.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Sharma into the device of Cheng ‘046 to design a memory device having a first memory element comprising of the transistor and the capacitor serially connected to each other and to add a second memory element having the same structure as the first memory element. The ordinary artisan would have been motivated to modify Cheng ‘046 in the manner set forth above for at least the purpose of using the transistor as a selecting switch that controls the electrical connection between a bit line (110) and a common plate of the capacitor (136; see Sharma ¶ [0030] ), so that the bit lines and the second memory element forms an array of memory elements in the device (see Abstract and ¶ [0022]-[0024]) for the further purpose of increasing the device density and reducing manufacturing cost of the device (¶ [0001], ¶ [0022], ¶ [0027] ).
Regarding claim 6, the memory device of claim 5, wherein the capacitor of the first memory element is coupled to the capacitor of the second memory element (see Sharma Fig. 1B and ¶ [0035]: “a group of platelines 130 connect the independent second capacitor plates of each capacitor 133, independent plates 135, to independent plates 135 of capacitors 133 below”).
Regarding claim 7, the memory device of claim 5, wherein the memory device is formed over a substrate (114; see Cheng ‘046 Fig. 15) and wherein the first memory element is laterally adjacent the second memory element relative to the substrate (Sharma Fig. 1A, when rotated 90-degrees counter clockwise, show the first memory element laterally adjacent the second memory element).
Regarding claim 8, the memory device of claim 5, wherein the device is formed over a substrate (Cheng ‘046 Fig. 15: 114) and wherein the first memory element is vertically adjacent the second memory element relatively to the substrate (Sharma Fig. 1A shows the first memory element on top of the second memory element).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng ‘046 (US 2018/0083046 A1) as applied to claim 9 above, and further in view of Cheng ‘144 (US 2022/0302144 A1).
Regarding claim 11, Cheng ‘046 teaches the method of claim 9, but does not teach the method wherein after providing the nanosheet, forming a dielectric to separate the nanosheet into a first region and second region, and wherein the transistor component is formed in a first portion of the first region of the nanosheet while a second transistor is formed in a first portion of the second region of the nanosheet.
Cheng ‘144, in the same field of invention, teaches a method wherein after providing the nanosheet (Figs. 1-7, ¶ [0028]-[0033] ), forming a dielectric (133, Fig. 9) to separate the nanosheet into a first region (left 2010&2020 in Fig. 20) and second region (right 2010&2020), and wherein the transistor component (left 2020) is formed in a first portion (upper left corner of Fig. 20) of the first region of the nanosheet while a second transistor (right 2020) is formed in a first portion (upper right corner of Fig. 20) of the second region of the nanosheet.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Cheng ‘144 into the method of form a dielectric after forming the nanosheet in order to separate the nanosheet into a first region and a second region, wherein the first transistor is in a portion of the first region and the second transistor is in a portion of the second region. The ordinary artisan would have been motivated to modify Cheng ‘046 et al. in the manner set forth above for at least the purpose of creating arrays of a memory element comprised of the transistor and the capacitor (¶ [0085]: 1T1C memory element ), with each memory element accessed through word lines and bit lines (see Fig. 20) and using the dielectric as a means to provide electrical insulation to prevent electrically shorting the components of the each memory element with each other.
Regarding claim 12, the method of claim 11 wherein the capacitor component is formed in a second portion (lower left of Chen ‘144 Fig. 20) of the first region of the nanosheet while a second capacitor (right 2010) is formed in a second portion (lower right of Fig. 20) of the second region of the nanosheet.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/JOHN M PARKER/Examiner, Art Unit 2899