Office Action Predictor
Last updated: April 15, 2026
Application No. 18/509,622

SEMICONDUCTOR DEVICE WITH RECESSED GATE AND METHOD FOR FABRICATING THE SAME

Non-Final OA §103
Filed
Nov 15, 2023
Examiner
KIM, SU C
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Nanya Technology Corporation
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
2y 9m
To Grant
62%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
695 granted / 899 resolved
+9.3% vs TC avg
Minimal -16% lift
Without
With
+-15.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
48 currently pending
Career history
947
Total Applications
across all art units

Statute-Specific Performance

§103
57.6%
+17.6% vs TC avg
§102
25.0%
-15.0% vs TC avg
§112
6.6%
-33.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 899 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. (US 20130302968) in view of Regarding claim 1, a method for fabricating a semiconductor device, comprising: providing a substrate 31 comprising a first peripheral region and a second peripheral region (Fig. 5); forming a mandrel layer 36 & 37 on the first peripheral region; conformally forming a layer of spacer material 39 on the substrate and covering the mandrel layer 36 & 37 (Fig. 5); forming an under layer 40 on the substrate 31 and covering the mandrel layer 36 & 37 and the plurality of sacrificial spacers 39; recessing the under layer to expose the mandrel layer 36 & 37 and the plurality of sacrificial spacers 39 (Fig. 7); selectively removing the plurality of sacrificial spacers to expose the first peripheral region (Fig. 8); forming a plurality of gate recesses in the first peripheral region 111 (Fig. 12); and forming a plurality of recessed gates 131-133on the plurality of gate recesses (Fig. 13). Lin fails to teach that performing a spacer etching process to turn the layer of spacer material into a plurality of sacrificial spacers on sides of the mandrel layer. However, Kim suggests that performing a spacer 220 etching process to turn the layer of spacer material into a plurality of sacrificial spacers on sides of the mandrel layer 210 (Fig. 2F). Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Lin with performing a spacer etching process to turn the layer of spacer material into a plurality of sacrificial spacers on sides of the mandrel layer as taught by Kim in order to reduce size of a device (recess gates, para. 0005 & 0056) and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art. Reclaim 2, Lin & Kim disclose that the layer of spacer material 39 is formed by atomic layer deposition (para. 0022, ALD). Allowable Subject Matter Claims 3-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SU C KIM/ Primary Examiner, Art Unit 2899
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Prosecution Timeline

Nov 15, 2023
Application Filed
Jan 08, 2026
Non-Final Rejection — §103
Mar 27, 2026
Response Filed

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604570
LIGHT-EMITTING DEVICE AND DISPLAY DEVICE HAVING SAME
2y 5m to grant Granted Apr 14, 2026
Patent 12585001
OPTICAL DETECTION APPARATUS AND OPTICAL DETECTION SYSTEM
2y 5m to grant Granted Mar 24, 2026
Patent 12581776
LIGHT EMITTING DIODE WITH HIGH LUMINOUS EFFICIENCY
2y 5m to grant Granted Mar 17, 2026
Patent 12581914
OPTICAL METROLOGY WITH NUISANCE FEATURE MITIGATION
2y 5m to grant Granted Mar 17, 2026
Patent 12563981
METHOD OF PROCESSING SUBSTRATE, SUBSTRATE PROCESSING APPARATUS, RECORDING MEDIUM, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
2y 5m to grant Granted Feb 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
62%
With Interview (-15.5%)
2y 9m
Median Time to Grant
Low
PTA Risk
Based on 899 resolved cases by this examiner. Grant probability derived from career allow rate.

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