DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The prior art documents submitted by applicant in the Information Disclosure Statement filed on 11/25/2023 has been considered and made of record.
Claim Objections
Claims 1 and 11 are objected to because of the following informalities: “on the same layer” may be interpreted in several ways, for instance, on the bottom or on the side of the same layer, which is not consistent with the drawings. Therefore, claims 1 and 11 will be interpreted as “part of the same layer”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitations: “a first semiconductor layer and a dummy semiconductor layer on the same layer”. There is insufficient antecedent basis for these limitations. For the purpose of examination, claim 1 will be interpreted as: A display device comprising: a substrate; a first semiconductor layer and a dummy semiconductor layer part of a same layer on a surface of the substrate and comprising the same material as each other; a second semiconductor layer overlapping the dummy semiconductor layer in a direction perpendicular to the surface of the substrate, the first semiconductor layer and the second semiconductor layer comprising different materials from each other; a first transistor comprising the first semiconductor layer, a first source electrode, and a first drain electrode, the first source electrode and the first drain electrode being connected to the first semiconductor layer; a second transistor comprising the second semiconductor layer, a second source electrode, and a second drain electrode, the second source electrode and the second drain electrode being connected to the second semiconductor layer; and a light-emitting element connected to the first transistor.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al., (United States Application Publication Number, US 2021/0202647 A1) hereinafter referenced as Wang.
Regarding claim 1, Wang teaches a display device comprising: a substrate (Fig.3A, element #110); a first semiconductor layer (Fig.3A, element #21) and a dummy semiconductor layer part of a same layer on a surface of the substrate (Fig.3, element #181, paragraph [0091], rows 3-4) and comprising the same material as each other (paragraph [0090], rows 7-10); a second semiconductor layer overlapping the dummy semiconductor layer in a direction perpendicular to the surface of the substrate (Fig.3A, element #31), the first semiconductor layer and the second semiconductor layer comprising different materials from each other ( paragraph [0074], rows 3-4, paragraph [0072], rows 4-5); a first transistor comprising the first semiconductor layer, a first source electrode, and a first drain electrode, the first source electrode and the first drain electrode being connected to the first semiconductor layer (Fig.3A, element #M1 has a source electrode, element #23, and a drain electrode, element #24 connected to element #21); a second transistor comprising the second semiconductor layer, a second source electrode, and a second drain electrode, the second source electrode and the second drain electrode being connected to the second semiconductor layer (Fig.3A, element #M2 has a source electrode, element #33, and a drain electrode, element #34 connected to element #31); and a light-emitting element connected to the first transistor (Fig.7, T1 is connected to OLED and T7 may be formed as similar to M1 of Fig.3A, paragraph [0110], row 15).
Regarding claim 2, Wang teaches the display device of claim 1 as set forth in the anticipation rejection. Wang further teaches the display device of claim 1, wherein the first semiconductor layer and the dummy semiconductor layer comprise same material. Wang further teaches some of the transistors may be implemented with an oxide semiconductor (paragraph [0056], rows 3-5) and the second semiconductor layer which is an oxide semiconductor, is IGZO (paragraph [0074], rows 11). Note that the first and second semiconductor layers can be switched since they both serve the same function of providing an active region for the transistors and this does not preclude one to implement both type of transistors as needed. Furthermore, a person skilled in the art would have been able to carry out the substitution, using the current process steps used for the deposition and pattern of the two semiconductor layers.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Park et al., (United States Application Publication Number, US 2020/0052056 A1) hereinafter referenced as Park.
Regarding claim 3, Wang teaches the display device of claims 1 and 2 as set forth in the anticipation rejection. Wang teaches the display device of claim 2, wherein the second semiconductor layer comprises IGZO (paragraph [0074], rows 11). Wang does not teach wherein the second semiconductor layer comprises indium tin gallium zinc oxide (ITGZO). Park teaches transistors wherein the semiconductor layer comprises ITGZO (paragraph [0016], rows 7-8). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Park and disclose wherein the second semiconductor layer comprises indium tin gallium zinc oxide, since this is one solution for the oxide semiconductor and would have had a reasonable expectation of success. Furthermore, a person skilled in the art would have been able to carry out the substitution of the two oxide layers. Finally, the substitution achieves the predictable result of providing an active region for the transistor. ITGZO can increase carrier concentration and conductivity as compare to IGZO and modify the bandgap.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Kim et al., (United States Application Publication Number, US 2021/0036028 A1) hereinafter referenced as Kim_028.
Regarding claim 10, Wang teaches the display device of claim 1 as set forth in the anticipation rejection. Wang further teaches the display device of claim 1, further comprising a light blocking layer between the substrate and the first semiconductor layer (Fig.3A, element #120 and #130a). Wang does not disclose wherein the first source electrode directly contacts the light blocking layer. Kim_028 discloses wherein the first source electrode directly contacts the light blocking layer (Fig.27, light blocking layer, element #360_2 is connected to the source). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Kim_028 and disclose wherein the first source electrode directly contacts the light blocking layer. As disclosed by Kim_028 this may increase the driving voltage range of the transistor (paragraph [0183] rows 8-9).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Kim et al., (United States Patent Number, US 9,147,719 B2) hereinafter referenced as Kim_719.
Regarding claim 11, Wang teaches the display device of claim 1 as set forth in the anticipation rejection. Wang does not explicitly teach the display device of claim 1, wherein the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are part of a same layer. Kim_719 discloses the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are part of a same layer (Fig.5F, elements #219a, #219b, 229a and #229b, column 11, rows 31-34). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Kim_719 and disclose the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are part of a same layer. As disclosed by Kim, this allows the source and drain electrodes of the two transistors to be deposited simultaneously (column 14, rows 55-60), which save processing time and reduces costs.
Allowable Subject Matter
Claims 4 is allowed if written in independent form. Claims 5-9 will be allowed as being dependent on claim 4. Claim 12 is allowed. Claims 13-20 are allowed as being dependent on claim 12.
The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 4, the cited prior art does not teach or fairly suggests, along with other
claimed features: “wherein the dummy semiconductor layer, the first gate insulating layer, and the second semiconductor layer have the same planar shape”.
Regarding claim 12, the cited prior art does not teach or fairly suggests, along with other claimed features: “the second semiconductor material comprises at least the same material as the first semiconductor material”.
Wang teaches a manufacturing method of a display device, the method comprising: forming a first semiconductor material on a substrate (Fig.3A, element #21 and #181 are formed on the substrate, element #110); forming a first gate insulating layer on the first semiconductor material (Fig.3A, element #12); forming a second semiconductor material on the first gate insulating layer (Fig.3A, element #31), and the dummy semiconductor layer overlapping the second semiconductor layer and a first semiconductor layer that does not overlap the second semiconductor layer (Fig.3A, element #181 overlaps element #31 and element #21 does not). Patterning the first and second semiconductor layers using lithography processes and etching steps to determine the shape and the relative location of active regions or other elements of transistors is well known in the art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gong et al, (United States Patent Application Publication Number, US 2023/0131513 A1) teaches the limitations of claims 1: “A display device comprising: a substrate; a first semiconductor layer and a dummy semiconductor layer on the same layer on a surface of the substrate and comprising the same material as each other; a second semiconductor layer overlapping the dummy semiconductor layer in a direction perpendicular to the surface of the substrate, the first semiconductor layer and the second semiconductor layer comprising different materials from each other; a first transistor comprising the first semiconductor layer, a first source electrode, and a first drain electrode, the first source electrode and the first drain electrode being connected to the first semiconductor layer; a second transistor comprising the second semiconductor layer, a second source electrode, and a second drain electrode, the second source electrode and the second drain electrode being connected to the second semiconductor layer” (Fig.2)
Yamazaki (United States Patent Application Publication Number, US 2020/0227561 A1) teaches the limitation of claims 6: “a thickness of a portion of the second semiconductor layer overlapping the second gate insulating layer is thicker than a thickness of a portion of the second semiconductor layer that does not overlap the second gate insulating layer” (Fig.2A, second semiconductor layer, element #230C and second gate insulating layer, element #250).
Ohta (United States Patent Number, US 12,224,356 B2) and Morosawa et al., (United States Patent Number US 9,859,437 B2) both teach the limitation of claim 8: “a portion of the first semiconductor layer overlapping the first gate insulating layer is thicker than a portion of the first semiconductor layer that does not overlap the first gate insulating layer” (Ohta, Fig.5, semiconductor layer, element #7L, first gate, element #11; Morosawa, Fig.1, semiconductor layer, element #20, first gate, element #40).
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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