DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 11/15/2023. Claims 1-20 are pending for this examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed on 01/04/2024.
Oath/Declaration
The oath or declaration filed on 11/15/2023 is acceptable.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-9 and 14-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding Claim 3, The instant claims recite limitation “a storage capacitor comprising a first capacitor electrode integrally provided with the first gate electrode and a second capacitor electrode integrally provided with the second gate electrode” is not clear because how first capacitor electrode integrally provided with the first gate electrode and a second capacitor electrode integrally provided with the second gate electrode is not defined. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Regarding Claim 14, The instant claims recite limitation “a storage capacitor comprising a first capacitor electrode integrally provided with the first gate electrode and a second capacitor electrode integrally provided with the second gate electrode” is not clear because how first capacitor electrode integrally provided with the first gate electrode and a second capacitor electrode integrally provided with the second gate electrode is not defined. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Claims 4-9 and 15-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, because of their dependency status from claims 3 and 14.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 10-11 and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LEE et al (US 2022/0366849 A1; hereafter LEE).
Regarding claim 1. LEE discloses a display apparatus comprising:
a substrate (Fig [1-4], substrate base layer BS, Para [ 0083]);
a first scan line (data line DL, Para [ 0050-0055]) on the substrate (Fig [1-4], substrate base layer BS, Para [ 0083]) and extending in a first direction (Fig [1-4]);
a semiconductor layer (transistor T1 , semiconductor region A1/D1/S1, Para [ 0090]) on the substrate (Fig [1-4], substrate base layer BS, Para [ 0083]), and comprising a first drain region (drain D1, Para [ 0090]), a first source region (source S1, Para [ 0090]) extending in the first direction so that a portion overlaps the first scan line (data line DL, Para [ 0050-0055]), and a driving active region (semiconductor region A1, Para [ 0090]) between the first drain region (drain D1, Para [ 0090]) and the first source region (source S1, Para [ 0090]);
a first gate electrode (upper gate G1-1, Para [ 0093]) on the semiconductor layer (transistor T1, semiconductor region A1/D1/S1, Para [ 0090]) and overlapping the driving active region (semiconductor region A1, Para [ 0090]);
a second gate electrode (lower gate G1-2, Para [ 0117]) under the semiconductor layer (transistor T1, semiconductor region A1/D1/S1, Para [ 0090]) and overlapping the driving active region (semiconductor region A1, Para [ 0090]); and
a first node connection line (node ND1/ELVDD, Para [ 0065-0066]) on the first gate electrode (upper gate G1-1, Para [ 0093]), electrically connected to the first gate electrode (upper gate G1-1, Para [ 0093]), and extending in a second direction that intersects the first direction (Fig [1-4], [Para [ 0060-0068]).
Regarding claim 2. LEE discloses the display apparatus of claim 1, LEE further discloses wherein, in a plan view, a portion of the first source region (source S1, Para [ 0090]) overlaps an area (Fig [2], [Para [ 0060-0068]) where the first scan line (data line DL, Para [ 0050-0055]) and the first node connection line intersect each other (node ND1/ELVDD, Para [ 0065-0066]).
Regarding claim 10. LEE discloses the display apparatus of claim 1, LEE further discloses wherein the second gate electrode (lower gate G1-2, Para [ 0117]) comprises a protrusion (lower gate G1-2, Para [ 0117]) overlapping an area where the first scan line (data line DL, Para [ 0050-0055]) and the first node connection line (node ND1/ELVDD, Para [ 0065-0066]) intersect each other in a plan view (Fig [2], [Para [ 0060-0068]).
Regarding claim 11. LEE discloses the display apparatus of claim 1, LEE further discloses wherein the semiconductor layer comprises an oxide semiconductor material (Para [ 0088-0091]).
Regarding claim 13. LEE discloses a display apparatus comprising:
a substrate (Fig [1-4], substrate base layer BS, Para [ 0083]);
a first scan line (data line DL, Para [ 0050-0055]) on the substrate and extending in a first direction (Fig [1-4], substrate base layer BS);
a semiconductor layer (transistor T1, semiconductor region A1/D1/S1, Para [0088- 0092]) on the substrate (Fig [1-4], substrate base layer BS), and comprising a first drain region (drain D1, Para [ 0090]), a first source region (source S1, Para [ 0090]), and a driving active region (semiconductor region A1, Para [ 0090]) between the first drain region (drain D1, Para [ 0090]) and the first source region (source S1, Para [ 0090]);
a first gate electrode (upper gate G1-1, Para [ 0093]) on the semiconductor layer and overlapping the driving active region;
a second gate electrode under the semiconductor layer (transistor T1, semiconductor region A1/D1/S1, Para [ 0090]) and overlapping the driving active region (semiconductor region A1, Para [ 0090]); and
a first node connection line (node ND1/ELVDD, Para [ 0065-0066]) on the first gate electrode (upper gate G1-1, Para [ 0093]), electrically connected to the first gate electrode (upper gate G1-1, Para [ 0093]), and extending in a second direction that intersects the first direction (Fig [2], [Para [ 0060-0068]), wherein the second gate electrode (lower gate G1-2, Para [ 0117]) comprises a protrusion (lower gate G1-2, Para [ 0117]) overlapping an area where the first scan line (data line DL, Para [ 0050-0055]) and the first node connection line (node ND1/ELVDD, Para [ 0065-0066]) intersect each other in a plan view (Fig [2], [Para [ 0060-0068])..
Regarding claim 19. LEE discloses the display apparatus of claim 13, LEE further discloses wherein the semiconductor layer comprises an oxide semiconductor material (Para [ 0088-0091]).
Allowable Subject Matter
Claims 12 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 12. a second driving voltage line extending in the second direction and on the first node connection line, and defining a hole overlapping the first node connection line.
Regarding claim 20. a second driving voltage line extending in the second direction and on the first node connection line, and defining a hole overlapping the first node connection line.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898