DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 04/14/2026. Claims 1-20 are pending for this examination.
Response to Arguments
Applicant’s reply filed on 04/14/2026, has been considered. Applicant’s amendments regarding claim 1, necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot. Applicant's arguments regarding claim 13 have been fully considered and found persuasive. A new search was conducted and no new art was found. Thus, claims 13-20 are allowed.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over LEE et al (US 2022/0366849 A1; hereafter LEE).
Regarding claim 1. LEE discloses a display apparatus comprising:
a substrate (Fig [1-5], substrate base layer BS, Para [ 0083]);
a first scan line (scan line scan line SL1i, Para [ 0061]) on the substrate (Fig [1-5], substrate base layer BS, Para [ 0083]) and extending in a first direction (Fig [1-5], scan line scan line SL1i, Para [ 0061]);
a semiconductor layer (transistor T2 , semiconductor region A2/D2/S2, Para [0067, 0090]) on the substrate (Fig [1-5], substrate base layer BS, Para [ 0083]), and comprising a first drain region (drain D2, Para [ 0090-0092]), a first source region (source S2, Para [ 0090-0092]) extending in the first direction so that at least a portion of the first source region (source S2, Para [ 0090]) overlaps the first scan line (Fig [1-5], scan line SL1n, Para [ 0061]), and a driving active region (semiconductor region A2, Para [ 0090-0092]) between the first drain region (drain D1, Para [ 0090]) and the first source region (source S1, Para [ 0090]);
a first gate electrode (upper gate G2-1, Para [ 0093]) on the semiconductor layer (transistor T2, semiconductor region A2/D2/S2, Para [ 0090]) and overlapping the driving active region (semiconductor region A2, Para [ 0090]);
a second gate electrode (lower gate G1-2, Para [ 0117]) under the semiconductor layer (transistor T2, semiconductor region A2/D2/S2, Para [ 0090]) and overlapping the driving active region (semiconductor region A1, Para [ 0090]); and
a first node connection line (Fig 5, voltage line VL1, Para [ 0126]) on the first gate electrode (Transistor T2, upper gate G1-1, Para [ 0093]), electrically connected to the first gate electrode (upper gate G1-1, Para [ 0093]), and extending in a second direction that intersects the first direction (Fig [1-4], [Para [ 0060-0068]).
But LEE first embodiment does not disclose explicitly a first source region extending in the first direction so that at least a portion of the first source region overlaps the first scan line in a plan view.
However, LEE discloses another embodiment a first source region extending in the first direction so that at least a portion of the first source region overlaps the first scan line in a plan view (Fig 6A-6F, scan line overlap transistors in plan view, Para [ 0116-0137]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine LEE teaching “a first source region extending in the first direction so that at least a portion of the first source region overlaps the first scan line in a plan view (Fig 6A-6F, scan line overlap transistors in plan view, Para [ 0116-0137])” for further advantage such as exhibiting low consumption and high reliability, and the scan driver that drives the scan line, ensures to simplify the structure and manufacturing process of the display device..
Regarding claim 11. LEE discloses the display apparatus of claim 1, LEE further discloses wherein the semiconductor layer comprises an oxide semiconductor material (Para [ 0088-0091]).
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over LEE et al (US 2022/0366849 A1; hereafter LEE) as applied clams above and further in view of JEONG et al (US 2024/0090276 A1; hereafter JEONG).
Regarding claim 3. LEE discloses the display apparatus of claim 1, But, LEE does not disclose explicitly further comprising a storage capacitor comprising a first capacitor electrode integrally provided with the first gate electrode in a plan view, and a second capacitor electrode integrally provided with the second gate electrode in a plan view.
In a similar field of endeavor, JEONG discloses a storage capacitor (Cst capacitor, Para [ 0279-0299]) comprising a first capacitor electrode (Fig 13-14, capacitor electrode PLT2a, Para [ 0316]) integrally provided with the first gate electrode ( gate G1) in a plan view, and a second capacitor electrode (Fig 13-14, capacitor electrode PLT2b, Para [ 0316]) integrally provided with the second gate electrode (PLT3) in a plan view (Fig 13-14, Para [ 0215, 0355]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine LEE in light of JEONG teaching “a storage capacitor (Cst capacitor, Para [ 0279-0299]) comprising a first capacitor electrode (Fig 13-14, capacitor electrode PLT2a, Para [ 0316]) integrally provided with the first gate electrode ( gate G1) in a plan view, and a second capacitor electrode (Fig 13-14, capacitor electrode PLT2b, Para [ 0316]) integrally provided with the second gate electrode (PLT3) in a plan view (Fig 13-14, Para [ 0215, 0355])” for further advantage such as transistors having a structure capable of providing desired performance.
Regarding claim 4. LEE and JEONG disclose the display apparatus of claim 3, JEONG further discloses wherein the second capacitor electrode is electrically connected to the first source region (Fig 13-14, Para [ 0279-0299]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine LEE in light of JEONG teaching “a storage capacitor (Cst capacitor, Para [ 0279-0299]) comprising a first capacitor electrode (Fig 13-14, capacitor electrode PLT2a, Para [ 0316]) integrally provided with the first gate electrode ( gate G1) in a plan view, and a second capacitor electrode (Fig 13-14, capacitor electrode PLT2b, Para [ 0316]) integrally provided with the second gate electrode (PLT3) in a plan view (Fig 13-14, Para [ 0215, 0355])” for further advantage such as transistors having a structure capable of providing desired performance.
Allowable Subject Matter
Claims 2, 5-10, 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 2. wherein, in a plan view, a portion of the first source region overlaps an area where the first scan line and the first node connection line intersect each other.
Regarding claim 5. wherein the storage capacitor further comprises a third capacitor electrode on the substrate and a fourth capacitor electrode between the third capacitor electrode and the second capacitor electrode, wherein the first capacitor electrode is electrically connected to the fourth capacitor electrode, and the second capacitor electrode is electrically connected to the third capacitor electrode.
Claims 6-9 are objected based on the dependency of claim 5
Regarding claim 10. wherein the second gate electrode comprises a protrusion overlapping an area where the first scan line and the first node connection line intersect each other in a plan view.
Regarding claim 12. a second driving voltage line extending in the second direction and on the first node connection line, and defining a hole overlapping the first node connection line.
Claims 13-20 are allowed.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
a second gate electrode under the semiconductor layer and overlapping the driving active region; and a first node connection line on the first gate electrode, electrically connected to the first gate electrode, and extending in a second direction that intersects the first direction, wherein the second gate electrode comprises a protrusion overlapping an area where the first scan line and the first node connection line intersect each other in a plan view, as recited in claim 13.
Claims 14-20 are allowed based on the dependency of claim 13.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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