DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/15/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US PG Pub 2024/0203925 (“Chiu”).
Regarding Claim 1, Chiu discloses an electronic device, comprising:
a first electronic component with a first technology node (14, Fig. 1) [0023]; and
a second electronic component with a second technology node different from the first technology node [0023]; and
a reinforcing component (130/140) supporting the first electronic component and the second electronic component,
wherein the first electronic component has an upper surface facing the reinforcing component and a lower surface configured to receive a first power [0021].
Regarding Claim 2, Chiu discloses the electronic device of Claim 1, wherein the reinforcing component is electrically connected to the first electronic component and the second electronic component (Fig. 1).
Regarding Claim 3, Chiu discloses the electronic device of Claim 1, wherein the second electronic component has an upper surface facing the reinforcing component and a lower surface configured to receive a second power different from the first power (Fig. 1).
Regarding Claim 4, Chiu discloses the electronic device of Claim 1, wherein the reinforcing component includes a data storage component [0023].
Regarding Claim 5, Chiu discloses the electronic device of Claim 1, further comprising:
a power delivery circuit (180) connected to a logic region of the first electronic component, wherein the power delivery circuit has a surface defined as a lower surface of the first electronic component (Fig. 1).
Regarding Claim 6, Chiu discloses the electronic device of Claim 5, wherein the first electronic component comprises a base portion and a conductive via at least partially disposed within the base portion, and the conductive via is electrically connected to the logic region and the power delivery circuit (Fig. 1).
Regarding Claim 7, Chiu discloses the electronic device of Claim 6, wherein the base portion comprises a silicon portion [0021](TSV).
Regarding Claim 8, Chiu discloses the electronic device of Claim 5, further comprising:
an encapsulant (160) encapsulating the first electronic component, the power delivery circuit, and the second electronic component.
Regarding Claim 9, Chiu discloses the electronic device of Claim 8, further comprising:
a circuit structure (180) disposed under the encapsulant, the first electronic component, the second electronic component, wherein the circuit structure is configured provide the first electronic component and the second electronic component with a power transmission path.
Regarding Claim 10, Chiu discloses the electronic device of Claim 9, wherein the circuit structure provides the first electronic component, the second electronic component, and the reinforcing component with an external non-power transmission path (Fig. 1).
Regarding Claim 11, Chiu discloses the electronic device of Claim 1, wherein the reinforcing component comprises a conductive element configured to provide the electronic device with an electrical path to an external device (Fig. 1).
Regarding Claim 12, Chiu discloses the electronic device of Claim 8, further comprising:
a conductive element (170) spaced apart from the first electronic component and the second electronic component, wherein the conductive element passes through the encapsulant and is configured to provide the electronic device with an electrical path to an external device (Fig. 1).
Regarding Claim 13, Chiu discloses the electronic device of Claim 8, wherein a portion of the encapsulant is disposed under the power delivery circuit (Fig. 1).
Regarding Claim 14, Chiu discloses the electronic device of Claim 1, further comprising:
an encapsulant encapsulating the first electronic component and the second electronic component, wherein the encapsulant and a lower surface of the first electronic component define a step (Examiner considers potential underfill to comprise a planarization layer as it acts to compensate for the height difference of the dies in a manner as utilized by Applicant [0030]); and
a planarization layer at least partially disposed on the step and has a planar surface disposed under the first electronic component and the encapsulant since an underfill can expand beyond the chip and solder bumps it is immediately proximate to.
Regarding Claim 15, Chiu discloses an electronic device, comprising:
a first chiplet (14, Fig.1);
a second chiplet (14); and
a data storage component (12, [0023]) configured to communicate with the first chiplet and the second chiplet,
wherein the first chiplet has an upper surface facing the data storage component and a lower surface configured to receive a power [0021].
Regarding Claim 16, Chiu discloses the electronic device of Claim 15, further comprising:
an encapsulant encapsulating the first chiplet and the second chiplet, wherein the encapsulant defines a first recess exposing the first chiplet and a second recess exposing the second chiplet (Fig. 1; upper surface of dies 14).
Regarding Claim 17, Chiu discloses the electronic device of Claim 16, further comprising:
a planarization layer disposed within the first recess and the second recess, wherein a portion of the planarization layer is disposed under the encapsulant (Examiner considers potential underfill to comprise a planarization layer as it acts to compensate for the height difference of the dies in a manner as utilized by Applicant [0030]).
Regarding Claim 18, Chiu discloses the electronic device of Claim 17, further comprising:
a power delivery circuit (180) disposed under the planarization layer and the data storage component; and
a conductive element disposed within the planarization layer and electrically connected to the power delivery circuit and the first chiplet (Fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu in view of US PG Pub 2024/0030174 to Olson et al (hereinafter Olson).
Regarding Claim 19, Chiu discloses an electronic device, comprising:
a reinforcement component (130/140; Fig.1);
a first electronic component (14) supported by the reinforcement component and having a backside power delivery circuit [0021]; and
a second electronic component (14) supported by the reinforcement component and spaced apart from the first electronic component [0021].
Chiu does not disclose wherein an edge of the first electronic component is slanted with respect to an edge of the second electronic component in a bottom view.
Olson discloses two electronic components being in a same plane but having different orientations relative to each other such that an edge of one component is slanted with respect to the other (Fig. 12B).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the chip package of Olson such that the edge of one component has an edge slanted with respect to the other component’s edge. Such an orientation may result unintentionally through a die shit or intentionally through die rotation (Olson, [0135]). A die rotation might be beneficial for various reasons such as routing configurations.
Regarding Claim 20, the combination of Chiu and Olson makes obvious the electronic device of Claim 19, wherein an imaginary line passing through a geometry center of the first electronic component and a geometry center of the second electronic component is slanted with respect to an edge of the reinforcement component (Olson, Fig. 12B).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893
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