Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group 1 Species I.C in the reply filed on 05/26/2026 is acknowledged. Claims 1-8 and 21-32 are still pending. Claims 5-6 and 22-23 are withdrawn.
Applicant first traverses the restriction between Invention I and II. Applicant argues that the restriction is improper on two grounds: first, that the product of claim 9 necessarily has dielectric layers, and so is connected to the method of claim 1; and second that Examiner did not provide any analysis of serious search and examination burden between Inventions I and II.
Regarding the first argument, Examiner only has to show that the product as claimed can be made by another and materially different process (emphasis added). In the present case, even if passivation layers are dielectric layers and interconnect structures have dielectric layers, this does not address the specific structure of the product as claimed in claim 9. Claim 9 specifically claims, for example, a first plurality of dielectric layers over the second passivation layer. This specific step is not mentioned in Claim 1. Even if the interconnect structure of Claim 1 has dielectric layers, it is in no way implied that these dielectric layers are “over” the second passivation layer.
Regarding the second argument, Examiner noted that the two inventions are classified in in separate places (Invention I in H10W20/01 and Invention II in H10W42/00.). Although Examiner did not explicitly state that this was the basis for establishing the search burden, it is a sufficient condition to establish the burden (see MPEP 808.02 – Note reason (A)).
Applicant next traverses the species restriction on two grounds: first, that the species Examiner cited are not mutually exclusive and that Examiner has not established a search and examination burden.
Regarding the first argument, Examiner noted the species disclosed based on the figures provided, not based on the claims. (806.04(e)). In this case, the Figures disclose distinct embodiments in Figs. 6A, 7A, and 8A. Regarding the claims, it is true that restriction between species is proper only if one claim recites limitations for a first species but not a second, which a second claim recites limitations for the second but not the first. In the present case, this is met at least with respect to claims 5 and 6, which are definitely mutually exclusive. The issue seems to be Fig. 8a and the interpretation of “step shape” in Claim 1. From what Examiner understands, Applicant is claiming that Fig. 8A can be viewed to read on claims 5, 6, and 7, rendering the restriction moot. Applicant argues that since Examiner marked claim 1 as generic, Examiner accepted the “step shape” language of that claim as generic as well, enabling Applicant to write claims 5, 6, and 7 as dependent on Claim 1, but allegedly all reading on Fig. 8A.
Examiner disagrees with the substance of this position. Clearly, Applicant intended three different configurations, as Figs. 6A, 7A, and 8A disclose unique configurations. Claims 5 and 6 are mutually exclusive. In Examiner’s view, the problem stems from Claim 1. Although Examiner noted that this claim was generic, Examiner was basing that conclusion on the dependent claims 5, 6, and 7 being separated out. Examiner did not look at the specific language of Claim 1. Upon consideration, Examiner is of the opinion that the step-shape language of claim 1 should preclude Fig. 8A from consideration. Although Applicant did indicate in the specification that Fig. 8A has a “stair step shape”, Examiner is of the view that a person of ordinary skill in the art would not describe the hill shape in Fig. 8A in this manner. Therefore, Examiner is issuing a 112(b) rejection for claim 7, but interpreting the claim (along with claim 1) to show a hill shape as indicated in Fig. 8A.
Regarding the second argument, Applicant states that Examiner has not shown a serious search burden. Applicant cites MPEP 808.02 which states “Where, however, the classification is the same and the field of search is the same and there is no clear indication of separate future classification and field of search, no reasons exist for dividing among independent or related inventions.” Applicant seems to be arguing that because the classification is the same and, according to the applicant, the field of sarch is the same, then restriction is improper. However, Examiner explicitly argued in the restriction that the field of search is not the same. According to the same MPEP section “Where it is necessary to search for one of the inventions in a manner that is not likely to result in finding art pertinent to the other invention(s) (e.g., searching different classes/subclasses or electronic resources, or employing different search queries), a different field of search is shown, even though the two are classified together. (Emphasis added by Examiner). In the restriction, Examiner argued that finding the different species would require different search queries. For example, finding a hill shaped conductive pad and finding a stair conductive pad require different keywords. Applicant has not disputed this. Therefore, in Examiner’s view, this condition has been met.
The requirement is still deemed proper and is therefore made FINAL.
Specification
The disclosure is objected to because of the following informalities:
In Para. [0032], Applicant states “the stair-step shape of metal pad 56S…”. In Examiner’s opinion, 56S should be 56SR.
In Para. [0039], Applicant describes the hill shape of metal pad 56SR as having a stair-step shape. As noted in the Election/Restrictions section above, Examiner finds this confusing, and is of the opinion that person of ordinary skill in the art would not describe the hill shaped structure in Fig. 8A as a stair-shape or step-shape.
Appropriate correction is required.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: Figs. 6C, 7C, and 8C do not show part 42, which is referenced in Paras. [0036], [0038], and [0040] with respect to these figures. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 28, 7, 24 and 32 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 4, the claim states in part “…an upper step along a major surface of the first passivation layer.” Examiner is unsure about the meaning of “major surface”, and the specification is silent on this except for repeating the claim language. For the purposes of this examination, Examiner is interpreting major to mean top.
A similar argument applies to claim 28.
Regarding Claims 7, 24, and 32, these claims all either recite or reference the hill structure of Fig. 8A, yet depend on claims which claim a stair-step structure. As noted in the Election/Restrictions section above, Examiner finds this language confusing, and is of the opinion that a person of ordinary skill in the art would not describe the hill-step structure as a step or stair-step structure. Thus, Examiner requests that Applicant rewrite the independent claims which recite the stair step structure, given that Applicant elected Fig. 8A. For the purposes of this examination, given that Applicant elected Fig. 8A, Examiner will examine these claims assuming this issue does not exist.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 21 is rejected under 35 U.S.C. 102a1 as being anticipated by US20160118352A1 (Ishii).
Regarding Claim 21, Ishii discloses a method (Para. [0166]) comprising: forming an active device on a front-side of a semiconductor substrate (Fig. 14, Para. [0168]); forming first dielectric layers and first metallization layers over the semiconductor substrate, the first metallization layers being electrically connected to the active device (Figs. 16-21; Paras. [0170-0174] – IL are the first dielectric layers and WL1 are the first metallization layers which are connected to the transistor TR through PLG1 – see Para. [0170]); forming second metallization layers within the first dielectric layers, the second metallization layers forming a ring around the first metallization layers and being electrically insulated from the first metallization layers (Figs. 16-21; Para. [0170-0174] – MP1 are the second metallization layers, which are in the ring region and form a seal ring around the first metallization layers, and are electrically insulated from the first metallization layers through STI – see Fig. 21 for example); forming a first metal pad over and electrically connected to the first metallization layers, the first metal pad comprising, in a cross-section, a U-shape with a left arm and a right arm (Figs. 23-24, pad PD is the first metal pad and has a U-shape in cross section – see annotated Fig. 24 below); forming a second metal pad over and electrically connected to the second metallization layers, the second metal pad forming a ring around the first metal pad, the second metal pad comprising, in the cross-section, a left portion adjacent to the left arm and a right portion adjacent to the right arm, the left portion having a first stair-step shape and the right portion having a second stair-step shape, the second stair-step shape being a reflection of the first stair- step shape (Figs. 23-24; pad AMP is the second metal pad, which is electrically connected to the second metallization layers – see Para. [0176]. See annotated Fig. 24 below – since RR is a ring portion, it extends around the circuit region LR and AMP will extend all the way around PD. In the annotated Figure below, the right and left arms of PD is shown but only the right portion of AMP is shown. However, when AMP extends around PD, there will be a left portion on the other side); and forming second dielectric layers over the first dielectric layers and encapsulating the first metal pad and the second metal pad (Fig. 25, Para. [0177]).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Ishii in view of Yang.
Regarding Claim 1, Ishii discloses a method (Para. [0166]) comprising: forming an active device over a semiconductor substrate (Fig. 14, Para. [0168]), forming an interconnect structure over the active device (Figs. 15 – 21, Paras. [00169-0174]), the interconnect structure comprising a first portion of a seal ring over the semiconductor substrate (Figs. 15 – 21, Para. [0166] which describes the ring region RR, where the seal ring is formed – see Para. [0176] which states that the seal ring includes the plugs PLG2, and metal patterns MP1-6, which are in the interconnect structure), the seal ring being electrically insulated from the active device (see Fig. 3, for example, which shows field insulting film STI which insulates the transistor TR from the ring region), forming a first insulating layer over the interconnect structure (Fig. 22, el. IL7, Para. [0175]); forming a first metal pad and a second metal pad extending through the first insulating layer and over the interconnect structure (Fig. 23 and 24, which show first metal pad PD and second metal pad AMP extending through the insulating layer and over the interconnect structure, Para. [0176]), the first metal pad having a bowl shape, the second metal pad having a step shape (Fig. 24); and depositing a passivation layer over the first metal pad and the second metal pad (Fig. 25, el. PAS, Para. [ 0177]).
Ishii does not disclose a plurality of active devices, and does not disclose that the first insulating layer is a passivation layer.
Yang discloses a semiconductor device (Fig. 4, Para. [0017]) with an interconnect structure (Fig. 4, els. 316A and 316B, Para. [0020] that comprise a seal ring (Fig. 4, el. 304, Para. [0020])), with a passivation layer over the interconnect structure (Fig. 4, el. 322, Para. [0026]). Yang also discloses a plurality of active devices (Para. [0019]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to substitute the insulating layer of Ishii with the passivation layer of Yang. As disclosed by Yang, adding a passivation layer at this location has the benefit of preventing or decreasing moisture, mechanical, and radiation damage to the integrated circuits (Para. [0026]). It would also have been obvious to include a plurality of active devices, as disclosed by Yang. This has the benefit of allowing for more configurations and functionality of the circuit.
Regarding Claim 2, Ishii in view of Yang discloses the method of Claim 1, wherein the first metal pad is electrically connected to the active devices (Ishii, see Fig. 3, for example, where PD is connected to PLG1 and TR through wirings WL1 (Ishii, Para. [0059]).
Regarding Claim 3, Ishii in view of Yang discloses the method of Claim 1, wherein the second metal pad is a second portion of the seal ring (Ishii, Para. [0098] which states that the seal ring SR includes the second metal pad AMP).
Regarding Claim 4, Ishii in view of Yang discloses the method of Claim 1, wherein the step shape of the second metal pad comprises a lower step embedded in the passivation layer and an upper step along a major (see 112(b) rejection above for claim interpretation) surface of the first passivation layer (Ishii, Fig. 3, which shows a lower portion of AMP in the insulating layer, and an upper portion on the surface of the insulating layer).
Claims 28 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Ishii in view of Yang.
Regarding Claim 28, Ishii discloses a method of forming a semiconductor device (Para. [0166]), comprising: forming an active device along a front-side of a semiconductor substrate (Fig. 14, Para. [0168]), the semiconductor substrate having a perimeter region surrounding the active device (ring region RR is a perimeter region that surrounds the active device – Para. [0166]); forming an interconnect structure over the semiconductor substrate (Figs. 15 – 21, Paras. [00169-0174]), the interconnect structure comprising first metallization layers electrically connected to the active device (WL1 are the first metallization layers, and are connected to the active device TR through PLG1 – see Fig. 18 and Para. [0171] for example) and a conductive seal ring extending along the perimeter region (Para. [0176] – seal ring SR extends along the perimeter region), the conductive seal ring being electrically isolated from the first metallization layers (see Fig. 23, for example, where region STI is an insulating region); forming a first insulation layer over the interconnect structure (Fig. 22, el. IL7, Para. [0175]); patterning the first insulating layer to form a first opening exposing one of the first metallization layers and a second opening exposing the conductive seal ring (Fig. 24, Para. [0176]); forming a first metal pad electrically connected to the one of the first metallization layers, the first metal pad having a bowl shape extending into the first opening (Fig. 24, pad PD is the first metal pad, which is connected to WL1 and has a bowl shape (Para. [0176]); forming a second metal pad electrically connected to the conductive seal ring, the second metal pad having a stair-step shape comprising a lower step extending into the second opening and an upper step extending along a major surface of the first passivation layer adjacent to the second opening (Fig. 24, where second metal pad AMP has a lower step extending into the second opening and upper step along a first surface of the insulating layer); and depositing a first passivation layer over the first metal pad and the second metal pad, the upper step of the second metal pad being embedded in the second passivation layer (Fig. 25, Para. [0177]).
Ishii does not disclose a plurality of active devices, and does not disclose that the first insulating layer is a passivation layer.
Yang discloses a semiconductor device (Fig. 4, Para. [0017]) with an interconnect structure (Fig. 4, els. 316A and 316B, Para. [0020] that comprise a seal ring (Fig. 4, el. 304, Para. [0020])), with a passivation layer over the interconnect structure (Fig. 4, el. 322, Para. [0026]). Yang also discloses a plurality of active devices (Para. [0019]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to substitute the insulating layer of Ishii with the passivation layer of Yang. As disclosed by Yang, adding a passivation layer at this location has the benefit of preventing or decreasing moisture, mechanical, and radiation damage to the integrated circuits (Para. [0026]). It would also have been obvious to include a plurality of active devices, as disclosed by Yang. This has the benefit of allowing for more configurations and functionality of the circuit.
Regarding Claim 31, Ishii in view of Yang discloses the method of claim 28, wherein the conductive seal ring forms a closed loop surrounding the active devices in a plan view of the semiconductor substrate, and wherein the second metal pad forms a ring surrounding the first metal pad in the plan view of the semiconductor substrate (Ishii, Fig. 2, which shows the ring region RR surrounding the chip region CR in plan view; also see Claim 1 of Ishii where the seal ring surrounds an integrated circuit in plan view. Since the seal ring comprises the second metal pad AMP, both the seal ring and the second metal pad will surround the device and first metal pad).
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Ishii in view of Yang and US20200135664A1 (Tseng).
Regarding Claim 29, Ishii in view of Yang disclose the method of claim 28, wherein forming the first metal pad and the second metal pad comprise: depositing a conductor film on the insulating layer, and patterning the conductive film using photolithography and etching (Ishii, Para. [0175]).
Ishii in view of Yang do not disclose wherein forming the first metal pad and forming the second metal pad comprise: depositing a metal seed layer over the first passivation layer and into the first opening and the second opening; forming a patterned plating mask over the metal seed layer, the patterned plating mask aligning with a sidewall of the second opening; plating a conductive material on portions of the metal seed layer exposed by the patterned plating mask; removing the patterned plating mask; and removing the portions of the metal seed layer that are not covered by the conductive material.
Tseng discloses a method (Figs. 2 -15, Para. [0022]), the method comprising depositing a metal seed layer over a first passivation layer and into a first opening and a second opening (Fig. 6, Para. [0028]); forming a patterned plating mask over the metal seed layer, the patterned plating mask aligning with a sidewall of the second opening (Fig. 6, Para. [0028]); plating a conductive material on portions of the metal seed layer exposed by the patterned plating mask (Fig. 7, Para. [0029]); removing the patterned plating mask and removing the portions of the metal seed layer that are not covered by the conductive material (Fig. 8, Para. [0030]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to substitute the process of Tseng for the photolithography and etching process of Ishii. Both involve generating metal pads on an insulating layer, but do so by different means to arrive at the same spot. This is an example of a simple substitution of one known element (the process of Tseng) for another (the process of Ishii) to achieve predictable results (metal pads covering holes)
Allowable Subject Matter
Claims 7, 24 and 32 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement for indicating allowable subject matter:
Regarding Claim 7, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination wherein the step shape of the second metal pad comprises an additional lower step embedded in the first passivation layer, and wherein the upper step is laterally interposed between the lower step and the additional lower step.
Regarding Claim 24, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination wherein each of the first stair-step shape and the second stair-step shape is a hill step comprising an upper step laterally interposed between a first lower step and a second lower step.
Regarding Claim 32, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination wherein the stair-step shape comprises a hill step, the hill step comprising the lower step, the upper step, and an additional lower step extending into an additional opening in the first passivation layer over the conductive seal ring, the upper step being laterally interposed between the lower step and the additional lower step.
Claims 8, 25-27, and 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 8, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination attaching a carrier substrate to the second passivation layer;attaching a package component to a back-side of the semiconductor substrate, the package component being electrically connected to the active devices;removing the carrier substrate; andforming an electrical connector over the second passivation layer and electrically connected to the first metal pad.
Regarding Claim 25, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination forming an electrical connector extending through the second dielectric layers, the electrical connector being electrically connected to the first metal pad.
Regarding Claim 26, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination forming a through via extending from the front-side of the semiconductor substrate to a back-side of the semiconductor substrate; andattaching an integrated circuit die to the semiconductor substrate, the integrated circuit die being electrically connected to the through via.
Regarding Claim 27, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination a third metal pad having an additional U-shape; anda fourth metal pad forming a ring around the third metal pad, the fourth metal pad having, in the cross-section, a third stair-step shape and a fourth stair-step shape that is a reflection of the third stair-step shape.
Regarding Claim 30, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination after removing the patterned plating mask and before removing the portions of the metal seed layer that are not covered by the conductive material, performing an anisotropic etching process to remove a lip of the conductive material extending laterally over the major surface of the first passivation layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROHIT PARTHASARATHY whose telephone number is (571)272-2572. The examiner can normally be reached Monday-Friday 8:30a-5p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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