Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/15/2023 was filed before the mailing date of the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1-20 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of copending Application No. 18/166,479 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because similar subject matter is claimed (see below).
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Instant application:
A memory device, comprising:
a stack structure disposed over a substrate, wherein the stack structure at least
comprises a data storage layer vertically sandwiched between a word line and a metal layer;
a bit line penetrating through the stack structure; and
a selector layer laterally surrounding a sidewall of the bit line and contacting the
metal layer.
8. A method of forming a memory device, comprising:
forming a stack structure over a substrate, wherein the stack structure
sequentially comprises: a first dielectric layer, a data storage layer, a conductive layer,
and a second dielectric layer;
forming an opening in the stack structure to expose sidewalls of the first
dielectric layer, the data storage layer, the conductive layer, and the second dielectric
layer;
laterally etching the sidewall of the conductive layer to form a first recess among
the conductive layer, the data storage layer, and the second dielectric layer;
forming a third dielectric layer in the first recess;
laterally etching the sidewall of the first dielectric layer to form a second recess
between the first dielectric layer and the data storage layer;
forming a metal layer in the second recess; and
forming a conductive pillar and a selector layer laterally surrounding a sidewall
of the conductive pillar in the opening.
16. A memory device, comprising:
a stack structure disposed over a substrate, wherein the stack structure at least
comprises:
a variable resistive structure comprising a variable resistive layer and a
contact layer; and
a word line structure disposed on the variable resistive structure;
a bit line penetrating through the stack structure; and
a selector layer laterally surrounding a sidewall of the bit line and contacting the
contact layer.
18/166,479:
A semiconductor device, comprising:
a first conductive layer;
a memory layer surrounding the first conductive layer;
a second conductive layer aside the memory layer; and
a selector layer on the second conductive layer, wherein a first side of the second conductive layer is covered by the memory layer, a second side of the second conductive layer is covered by the selector layer, and a third side of the second conductive layer is exposed by the selector layer.
10. A semiconductor device, comprising:
a first conductive line extending along a first direction;
a second conductive line extending along a second direction substantially perpendicular to the first direction;
a third conductive line extending along a third direction substantially perpendicular to the first direction and the second direction, and electrically connected to the first conductive line;
a memory layer surrounding the third conductive line; and
a first selector pillar extending along the third direction and disposed between the memory layer and the second conductive line.
16. A method of forming a semiconductor device, comprising:
forming a stack comprising a plurality of first dielectric layer, a plurality of first conductive layers and a plurality of second dielectric layers alternately arranged;
forming a first opening in the stack to penetrate through the first dielectric layers, the first conductive layers and the second dielectric layers;
recessing inner sidewalls of the first conductive layers through the first opening, to form a plurality of first recesses;
filling second conductive layers in the first recesses;
recessing inner sidewalls of the second dielectric layers through the first opening, to form a plurality of second recesses;
forming selector layers in the second recesses;
forming a memory layer on sidewalls of the first opening; and
filling the first opening with a conductive layer.
In regards to the differences, the nomenclature is slightly different. The “first’ conductor layer equate to the bit line, the “second” conductive layer equates to the metal layer, and the “third” conductive layer equates to a second bit line which is conventionally done in the art of RRAM.
Note: Dependent claims not repeated for brevity of office action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL LEBENTRITT whose telephone number is (571)272-1873. The examiner can normally be reached IFP Mon- Fri 8:30 am- 6 pm.
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MICHAEL . LEBENTRITT
Primary Examiner
Art Unit 2893
/MICHAEL LEBENTRITT/ Primary Examiner, Art Unit 2893
Prosecution Insights