DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species B, sub-species 1, with claims 1, 3, 9-11, 13-14, 18, 20-21, 24-26, 30, 33, 35, and 39-41 indicated by Applicant to read thereon, in the reply filed on 31 July 2026 is acknowledged. The traversal is on the grounds that 1) the sub-species identification appears to be incorrect, 2) the election requirement fails to show that the identified species are independent and distinct, 3) a showing of serious burden has not been made, 4) the election requirement is based on the incorrect assertion that all of the species are mutually exclusive, and 5) the demarcation between species is arbitrary, without regard to common aspects between species.
This is not found persuasive because:
1) Species and sub-species identification were based on the inventions presented in the application, and they have been described using documentation from the applicant.
2) A species restriction does not require both independent and distinct inventions — it can apply to either independent species or distinct species that are related as disclosed but still patentably distinct as claimed. There is no requirement for both: MPEP § 806.06 and § 808.01(a) clarify that restriction can be required for either type of species relationship.
3) A serious search/examination burden if not restricted. See previous Office action “There is a serious search and/or examination burden for the patentably distinct species as set forth above because at least the following reason(s) apply:
- the species or groupings of patentably indistinct species have acquired a separate status in the art in view of their different classification;
- the species or groupings of patentably indistinct species have acquired a separate status in the art due to their recognized divergent subject matter;
- the species or groupings of patentably indistinct species require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries); and/or
- the prior art applicable to one group or species would not likely be applicable to another species”
4) The inventions in the application each possess a unique set of characteristics derived from their device structure. For example, since the electric field distribution is directly affected in blocking mode, the exact configuration and combination of the inclusion of device elements critically affect device function.
5) Again, the demarcation is based on the descriptions provided in the instant application. Conceptual evidence from the application was provided for each of the listed sub-species in the prior office action.
The requirement is still deemed proper and is therefore made FINAL.
While the examiner acknowledges that the applicant indicated that claims 1, 3, 9-11, 13-14, 18, 20-21, 24-26, 30, 33, 35, and 39-41 read on the elected species B, sub-species 1, claims 14 and 30 do not read on the elected species B because the elected species B at least fails to include a second JFET region.
Claims 14, 22-23, and 30 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species/subspecies, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 31 July 2026.
Claims 2, 4-8, 12, 15-17, 19, 27-29, 31-32, 34, 36-38, and 42-83 were previously cancelled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 9-11, 13, 18, 21, 24-26, 33, 35, 39-41 are rejected under 35 U.S.C. 103 as being unpatentable over Okumura (US 20200295141 A1, hereinafter “Okumura”), in view of Yuan (US 20240282810 A1, hereinafter “Yuan”).
Regarding Claim 1 – Okumura discloses a semiconductor device, comprising: a semiconductor layer structure ([0012] and Fig. 4) comprising a drift region having a first conductivity type (2 [0076] and Fig. 6), a well region having a second conductivity type on the drift region (6 [0076] and Fig. 6); and a first gate trench and a second gate trench that each extend into the semiconductor layer structure (16 [0071] and Fig. 6).
Okumura fails to disclose a first junction field effect ("JFET") pattern having the first conductivity type, wherein the first JFET pattern comprises a plurality of first JFET regions, where a first of the first JFET regions is below and vertically overlapping the first gate trench and a second of the first JFET regions is below and vertically overlapping the second gate trench, and wherein first conductivity dopant concentrations of the respective first and second of the first JFET regions each exceed a first conductivity dopant concentration of the drift region, and the first and second of the first JFET regions are spaced apart from each other.
However, Yuan discloses a first junction field effect ("JFET") pattern having the first conductivity type (17 [0061] and Fig. 9), wherein the first JFET pattern comprises a plurality of first JFET regions (A plurality of cells containing the first JFET region, Yuan [0064] and [0096]), where a first of the first JFET regions is below and vertically overlapping the first gate trench (as seen in Fig. 9) and a second of the first JFET regions is below and vertically overlapping the second gate trench (exactly as the first cell shown in Fig. 9, [0096]), and wherein first conductivity dopant concentrations of the respective first and second of the first JFET regions each exceed a first conductivity dopant concentration of the drift region (Doping concentration of 17 is greater than 11 [0102]), and the first and second of the first JFET regions are spaced apart from each other (Each 17 is aligned to each trench gate, with separation in between, Yuan Fig. 9).
Yuan discloses an analogous semiconductor device to Okumura. Yuan teaches a first junction field effect ("JFET") pattern having the first conductivity type vertically overlapping the gate trench for the benefit of overvoltage protection (Yuan [0065]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Okumura and Yuan to place a first junction field effect ("JFET") pattern having the first conductivity type vertically overlapping the gate trench for the benefit of overvoltage protection.
PNG
media_image1.png
398
583
media_image1.png
Greyscale
PNG
media_image2.png
427
570
media_image2.png
Greyscale
PNG
media_image3.png
376
548
media_image3.png
Greyscale
Regarding Claim 3 – Okumura modified by Yuan discloses all the limitations of claim 1.
The combination of Okumura and Yuan further discloses the semiconductor layer structure further comprises a trench shield having the second conductivity type that is in between a bottom of the first gate trench and the first of the first JFET regions (31, Yuan [0076] and Fig. 9).
Yuan discloses an analogous semiconductor device to Okumura. Yuan teaches a trench shield having the second conductivity type that is in between a bottom of the first gate trench and the first of the first JFET regions for the benefit of improved voltage endurance of the bottom of the trench gate (Yuan [0078]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Okumura and Yuan to place a trench shield having the second conductivity type that is in between a bottom of the first gate trench and the first of the first JFET regions for the benefit of improved voltage endurance of the bottom of the trench gate.
Regarding Claim 9 – Okumura modified by Yuan discloses all the limitations of claim 3.
The combination of Okumura and Yuan further discloses the semiconductor layer structure further comprises a first support shield and a second support shield that each have the second conductivity type and that each extend downwardly from the upper surface of the semiconductor layer structure into the drift region (combination of 3a and 8, Okumura [0071], [0077], and Fig. 6), where the first gate trench is in between the first support shield and the second support shield (Okumura Fig. 6).
Regarding Claim 10 – Okumura modified by Yuan discloses all the limitations of claim 9.
The combination of Okumura and Yuan further discloses the semiconductor layer structure further comprises a third JFET pattern that includes a plurality of third JFET regions having the first conductivity type (17, Okumura [0070] and Fig. 6), wherein a first of the third JFET regions is below and vertically overlaps the first support shield and a second of the third JFET regions is below and vertically overlaps the second support shield (Okumura Fig. 6).
Regarding Claim 11 – Okumura modified by Yuan discloses all the limitations of claim 10.
The combination of Okumura and Yuan further discloses the first of the third JFET regions is spaced-apart from the second of the third JFET regions (One on left and another in the center in Okumura Fig. 6, with separation shown).
Regarding Claim 13 – Okumura modified by Yuan discloses all the limitations of claim 11.
The combination of Okumura and Yuan further discloses an upper surface of the first of the first JFET regions is at a shallower depth in the semiconductor layer structure than upper surfaces of the first and second of the third JFET regions (Upper surfaces of 17 in Yuan above top of drift region (11 in annotated Yuan Fig. 9), while upper surfaces of 17 in Okumura below top of drift region (2 in Okumura Fig. 6)).
Regarding Claim 18 – Okumura discloses a semiconductor device, comprising: a semiconductor layer structure ([0012] and Fig. 4); and a plurality of gate trenches extending into the semiconductor layer structure (16 [0071] and Fig. 6), wherein the semiconductor layer structure comprises: a drift region having a first conductivity type (2 [0076] and Fig. 6); at least one well region having a second conductivity type on the drift region (6 [0076] and Fig. 6); a plurality of trench shields having the second conductivity type positioned below the respective gate trenches (4 [0071] and Fig. 6);
Okumura fails to disclose a first junction field effect ("JFET") pattern having the first conductivity type, the first JFET pattern comprising a plurality of spaced-apart first JFET regions that are positioned below and vertically overlaps the respective trench shields, wherein a first conductivity type dopant concentration of each first JFET region exceeds a first conductivity type dopant concentration of the drift region.
However, Yuan discloses a first junction field effect ("JFET") pattern having the first conductivity type (17 [0061] and Fig. 9), the first JFET pattern comprising a plurality of spaced-apart first JFET regions that are positioned below and vertically overlaps the respective trench shields (A plurality of cells containing the 17, Yuan [0064], [0096], with 17 overlapping 31, Yuan [0076] and Fig. 9), wherein a first conductivity type dopant concentration of each first JFET region exceeds a first conductivity type dopant concentration of the drift region (Doping concentration of 17 is greater than 11 [0102]).
Yuan discloses an analogous semiconductor device to Okumura. Yuan teaches a first junction field effect ("JFET") pattern having the first conductivity type vertically overlapping the shield under the gate trench for the benefit of overvoltage protection (Yuan [0065]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Okumura and Yuan to place a first junction field effect ("JFET") pattern having the first conductivity type vertically overlapping the shield under the gate trench for the benefit of overvoltage protection.
Regarding Claim 21 – Okumura modified by Yuan discloses all the limitations of claim 18.
The combination of Okumura and Yuan further discloses an upper surface of each first JFET region is self-aligned with a lower surface of a respective one of the trench shields (Yuan Fig. 9).
Regarding Claim 24 – Okumura modified by Yuan discloses all the limitations of claim 18.
The combination of Okumura and Yuan further discloses the semiconductor layer structure further comprises a current spreading layer having the first conductivity type in an upper portion of the drift region (5, Okumura [0072], [0075], and Fig. 6), and a first conductivity dopant concentration of the first JFET pattern exceeds a first conductivity dopant concentration of the current spreading layer (Doping concentration of 17 greater than 13, and 13 forms the current spreading layer 34 (also indicated by 100 in Fig. 9), Yuan [0090], [0102] and Figs. 10 and 18), and the first conductivity dopant concentration of the current spreading layer exceeds the first conductivity dopant concentration of the drift region (e.g. 5a (1E17cm-3) and 5b (1E17cm-3) exceed 2b (3E15cm-3), Okumura [0072]-[0075]).
PNG
media_image4.png
559
528
media_image4.png
Greyscale
PNG
media_image5.png
266
385
media_image5.png
Greyscale
Regarding Claim 25 – Okumura modified by Yuan discloses all the limitations of claim 24.
The combination of Okumura and Yuan further discloses an upper surface of each first JFET region is at a greater depth within the semiconductor layer structure than an upper surface of the current spreading layer (Upper surface of 17 deeper than upper surface of 34, Yuan Fig. 10).
Regarding Claim 26 – Okumura modified by Yuan discloses all the limitations of claim 18.
The combination of Okumura and Yuan further discloses the semiconductor layer structure further comprises a first support shield and a second support shield that each have the second conductivity type and that each extend downwardly from the upper surface of the semiconductor layer structure into the drift region (Combination of 3a and 8 on right and left sides of Okumura Fig. 6, [0071] and [0077]), and wherein a first of the gate trenches is in between the first support shield and the second support shield (9 and 10 in Okumura Fig. 6, [0080]-[0082]), and wherein the semiconductor layer structure further comprises a third JFET pattern that includes a plurality of third JFET regions having the first conductivity type (17, Okumura [0070] and Fig. 6), wherein a first of the third JFET regions is positioned below and vertically overlaps the first support shield and a second of the third JFET regions is positioned below and vertically overlaps the second support shield and spaced apart from the first of the third JFET regions (Okumura Fig. 6).
Regarding Claim 33 – Okumura discloses a semiconductor device, comprising: a semiconductor layer structure ([0012] and Fig. 4) comprising: a drift region having a first conductivity type (2 [0076] and Fig. 6); a current spreading layer having the first conductivity type and a first conductivity dopant concentration that exceeds a first conductivity dopant concentration of the drift region on the drift region (e.g. 5a (1E17cm-3) and 5b (1E17cm-3) exceed 2b (3E15cm-3), [0072]-[0075] and Fig. 6); a well region having a second conductivity type above the current spreading layer (6 [0076] and Fig. 6); and a gate trench extending into the semiconductor layer structure (16 [0071] and Fig. 6).
Okumura fails to disclose a first junction field effect ("JFET") pattern having the first conductivity type that has a lower surface that extends deeper into the semiconductor layer structure than a lower surface of the current spreading layer, where the first JFET pattern includes a plurality of spaced apart first JFET regions, each of which has a first conductivity dopant concentration that exceeds a first conductivity dopant concentration of the current spreading layer.
However, Yuan discloses a first junction field effect ("JFET") pattern having the first conductivity type that has a lower surface that extends deeper into the semiconductor layer structure than a lower surface of the current spreading layer (Lower surface of 17 lower than lower surface of 100, Yuan Fig. 9), where the first JFET pattern includes a plurality of spaced apart first JFET regions (A plurality of cells containing the 17, Yuan [0064], [0096], with 17 spaced apart, Yuan Fig. 9), each of which has a first conductivity dopant concentration that exceeds a first conductivity dopant concentration of the current spreading layer (Doping concentration of 17 is greater than 11 [0102]).
Yuan discloses an analogous semiconductor device to Okumura. Yuan teaches a first junction field effect ("JFET") pattern having the first conductivity type vertically overlapping the shield under the gate trench for the benefit of overvoltage protection (Yuan [0065]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Okumura and Yuan to place a first junction field effect ("JFET") pattern having the first conductivity type vertically overlapping the shield under the gate trench for the benefit of overvoltage protection.
Regarding Claim 35 – Okumura modified by Yuan discloses all the limitations of claim 33.
The combination of Okumura and Yuan further discloses the semiconductor layer structure further comprises a trench shield having the second conductivity type that is in between a bottom of the gate trench and a first of the first JFET regions (31, Yuan [0076] and Fig. 9).
Yuan discloses an analogous semiconductor device to Okumura. Yuan teaches a trench shield having the second conductivity type that is in between a bottom of the gate trench and a first of the first JFET regions for the benefit of improved voltage endurance of the bottom of the trench gate (Yuan [0078]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Okumura and Yuan to place a trench shield having the second conductivity type that is in between a bottom of the gate trench and a first of the first JFET regions for the benefit of improved voltage endurance of the bottom of the trench gate.
Regarding Claim 39 – Okumura modified by Yuan discloses all the limitations of claim 34.
The combination of Okumura and Yuan further discloses the semiconductor layer structure further comprises a first support shield and a second support shield that each have the second conductivity type and that each extend downwardly from the upper surface of the semiconductor layer structure into the drift region (combination of 3 and 8, Okumura [0071], [0077], and Fig. 6), where the gate trench is in between the first support shield and the second support shield (Okumura Fig. 6).
Regarding Claim 40 – Okumura modified by Yuan discloses all the limitations of claim 39.
The combination of Okumura and Yuan further discloses the semiconductor layer structure further comprises a third JFET pattern that includes a plurality of third JFET regions having the first conductivity type (17, Okumura [0070] and Fig. 6), wherein a first of the third JFET regions is positioned below the first support shield and a second of the third JFET regions is positioned below the second support shield (Okumura Fig. 6).
Regarding Claim 41 – Okumura modified by Yuan discloses all the limitations of claim 40.
The combination of Okumura and Yuan further discloses the first of the third JFET regions is spaced-apart from the second of the third JFET regions (One on the left and another in the center in Okumura Fig. 6, with separation shown).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Okumura (US 20200295141 A1, hereinafter “Okumura”), in view of Yuan (US 20240282810 A1, hereinafter “Yuan”), and further in view of Hoshi (US 20170141223 A1, hereinafter “Hoshi”).
Regarding Claim 20 – Okumura modified by Yuan discloses all the limitations of claim 18.
The combination of Okumura and Yuan fails to disclose each first JFET region directly contacts a respective one of the trench shields.
However, Hoshi discloses each first JFET region directly contacts a respective one of the trench shields (20 contacts 4, Hoshi [0044] and Fig. 1).
Hoshi discloses an analogous semiconductor device to Okumura. Hoshi teaches putting each first JFET region directly in contact with a respective one of the trench shields for the benefit of increasing the n-type impurity concentration, thereby reducing the overall on-resistance (Hoshi [0074]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Okumura and Hoshi to put each first JFET region directly in contact with a respective one of the trench shields for the benefit of increasing the n-type impurity concentration, thereby reducing the overall on-resistance.
PNG
media_image6.png
460
574
media_image6.png
Greyscale
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
