Prosecution Insights
Last updated: August 16, 2026
Application No. 18/510,756

ENHANCED ISOLATION FOR ON-CHIP CURRENT SENSORS

Non-Final OA §103
Filed
Nov 16, 2023
Examiner
LOPEZ, JORGE ANDRES
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Wolfspeed Inc.
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
31 granted / 33 resolved
+25.9% vs TC avg
Moderate +8% lift
Without
With
+8.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
28 currently pending
Career history
69
Total Applications
across all art units

Statute-Specific Performance

§103
67.6%
+27.6% vs TC avg
§102
19.4%
-20.6% vs TC avg
§112
13.0%
-27.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 33 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of “Group I and Species G (claims 1-8,12,14,16 and 17)” in the reply filed on 04/24/2026, is acknowledged. Applicant’s arguments regarding the species restriction are persuasive; therefore, the “Species A-I” restriction is hereby withdrawn. The restriction on inventions “Groups I and II” is without traverse; therefore, considered valid and made FINAL (please see Examiner’s arguments on invention Requirement for Restriction/Election filed on 02/19/2026) Claims 41 and 56 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Claims 1-18 and 31 remain pending, with claims 1 and 17 being independent. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4,6,9-11,13-14 and 16-18 are rejected under 35 U.S.C. 103 as being obvious over US 2023/0282741 A1; Kawahara et al.; 09/2023; (“741”). Regarding Claim 1. 741 teaches in Figs. 2 and 3 about a semiconductor device, comprising: a device active region (Fig. 3, region item 101) comprising a first well (Fig. 3, region item 101 comprises well item 30), at least a portion of the first well being part of a first metal-oxide-semiconductor field-effect transistor (MOSFET) (“a MOSFET … including a first well region”, Abstract paragraph, Ln. 3-4); and a sensor region (Fig. 3, region item 102) comprising a second well (Fig. 3, region item 102 comprises well item 31), at least a portion of the second well being part of a second MOSFET configured to mirror a current in the first MOSFET (“a MOSFET … including a second well region”, Abstract paragraph, Ln. 5-6), wherein a distance between an outer side edge of the second well and an inner side edge of the first well is constant (Fig. 2, the distance between the outer side edge of active region 102 and the inner side edge of active region 101 is constant). 741 does not teach about a semiconductor device, wherein a distance between an outer edge of the second well and an inner edge of the first well is constant or the distance decreases approaching one or more vertices of the second well. It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have adjusted the shape at the corner edges of the second well to maintain a constant distance between the first and second wells (or to decrease the same distance approaching one or more vertices of the second well), since it has been held that adjusting the shape of an article involves only routine skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04. Regarding Claim 2. 741 teaches in Fig. 3 about a semiconductor device, further comprising an isolation structure (item 32) between the first and second wells (item 32 is between well items 30 and 31). Regarding Claim 3. 741 teaches in Fig. 11 about a semiconductor device, wherein each of the first and second wells comprises material of a second conductivity type (“first well regions of a second conductivity type … second well region of a second conductivity type”, [0008], Ln. 7-17), and wherein the isolation structure comprises material of a first conductivity type (separation region item 26 as a part of the drift layer 20, wherein the “drift layer of a first conductivity type”, [0008], Ln. 5-6), the first conductivity type being opposite in polarity to the second conductivity type (“well region having a conductivity type opposite to that of a drift layer of the dummy sense region”, [0007], Ln. 14-16). Regarding Claim 4. 741 teaches in Fig. 11 about a semiconductor device, wherein the isolation structure is configured to electrically isolate the first and second wells (“the dummy sense region between the first well regions and the second well region, is separated from the first well regions and the second well region, and is not ohmic-connected to any of the source electrode and the sense pad”, [0008]. Ln. 33-37). Regarding Claim 6. 741 teaches in Fig. 11 about a semiconductor device, wherein the isolation structure is configured to provide a high-resistance electrical connection between the first and second wells (“the dummy sense region between the first well regions and the second well region, is separated from the first well regions and the second well region, and is not ohmic-connected to any of the source electrode and the sense pad”, [0008]. Ln. 33-37). Regarding Claim 9. 741 teaches in Fig. 2 about a semiconductor device, wherein each of the second well and the isolation structure are rectangular in shape and concentric with each other when viewed in plan view (items 102 and 103 are rectangular in shape and concentric with each other). 741 does not teach about a semiconductor device, wherein each of the second well and the isolation structure are circular in shape and concentric with each other when viewed in plan view. It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have adjusted the shape in plan view of the second well and the isolation structure (while maintaining concentricity in plan view), since it has been held that adjusting the shape of an article involves only routine skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04. Regarding Claim 10. 741 teaches in Fig. 2 about a semiconductor device, wherein each of the second well and the isolation structure are rectangular in shape when viewed in plan view (items 102 and 103 are rectangular in shape). 741 does not teach about a semiconductor device, wherein each of the second well and the isolation structure are rectangular in shape and have rounded corners when viewed in plan view. It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have adjusted the shape of the corners in plan view of the second well and the isolation structure, since it has been held that adjusting the shape of an article involves only routine skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04. Regarding Claim 11. 741 teaches in Fig. 2 about a semiconductor device, wherein a vertical and horizontal distance, in plan view, across the isolation structure between the first and second wells is constant (the vertical and horizontal distance in, plan view, across the isolation structure between the wells of items 101 and 102 is constant). 741 does not teach about a semiconductor device, wherein a distance, in plan view, across the isolation structure between the first and second wells is constant. It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have adjusted the shape of the corners in plan view of the first and second wells to maintain a constant distance between them, since it has been held that adjusting the shape of an article involves only routine skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04. Regarding Claim 13. 741 teaches in Fig. 2 about a semiconductor device, wherein a shape defined by the outer edge of the second well is different than a shape defined by the inner edge of the first well (the outer edge shape of the second well is the same as the shape defined by the inner edge of the first well). 741 does not teach about a semiconductor device, wherein a shape defined by the outer edge of the second well is different than a shape defined by the inner edge of the first well. It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have experimented with different shapes for the outer edge first well compared to the shape of the second well, since it has been held that adjusting the shape of an article involves only routine skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04. Regarding Claim 14. 741 teaches in Fig. 20 about a semiconductor device, wherein the isolation structure comprises a trench (item 99) that is at least partially filled with an insulating material (trench item 99 is at least partially filled with insulating material item 50). Regarding Claim 16. 741 teaches in Fig. 3 about a semiconductor device, wherein each of the first and/or second MOSFET comprises a plurality of unit cells (gate electrode items 60 in the first and/or second MOSFET comprise a plurality of unit cells connected in parallel, “although not shown in the drawings, the gate electrode 60 in the active region 101 and the gate electrode 60 in the active sense region are connected to each other, and these gate electrodes 60 are electrically connected via the gate pad 82”, [0049], Ln. 1-5). Regarding Claim 17. 741 teaches in Figs. 2 and 3 about a semiconductor device, comprising: a device active region (Fig. 3, region item 101) comprising a first well (Fig. 3, region item 101 comprises well item 30), at least a portion of the first well being part of a first metal-oxide-semiconductor field-effect transistor (MOSFET) (“a MOSFET … including a first well region”, Abstract paragraph, Ln. 3-4); and a sensor region (Fig. 3, region item 102) comprising a second well (Fig. 3, region item 102 comprises well item 31), at least a portion of the second well being part of a second MOSFET configured to mirror a current in the first MOSFET (“a MOSFET … including a second well region”, Abstract paragraph, Ln. 5-6), wherein, when viewed in plan view, the first well surrounds the second well and a distance between an outer edge of the second well and an inner edge of the first well at corners of the second well is greater to the distance between the outer edge of the second well and the inner edge of the first well at sides of the second well (Fig. 2, the distance at corners between the first and second wells is greater than the distance between outer side edges of active region 102 and inner side edges of active region 101). 741 does not teach about a semiconductor memory device, wherein, when viewed in plan view, the first well surrounds the second well and a distance between an outer edge of the second well and an inner edge of the first well at corners of the second well is less than or equal to the distance between the outer edge of the second well and the inner edge of the first well at sides of the second well. It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have adjusted the distance at corners between the first and second wells by adjusting their shape (including round corners and/or using higher or lower polygon shapes), since it has been held that adjusting the shape of an article involves only routine skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04. Regarding Claim 18. 741 teaches in Fig. 2 about a semiconductor device, wherein the outer edge of the second well and the inner edge of the first well at one or more corners of the second well are not rounded, such that a distance, in a plan view, between the first and second wells is not constant (distance between the first and second wells at corners is larger compared to side edges). 741 does not teach about a semiconductor memory device, wherein the outer edge of the second well and the inner edge of the first well at one or more corners of the second well are rounded, such that a distance, in a plan view, between the first and second wells is constant. It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have adjusted the distance at corners between the first and second wells by adjusting their shape (including round corners), since it has been held that adjusting the shape of an article involves only routine skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04. Allowable Subject Matter Claims 5,7-8,12,15 and 31 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art does not teach or suggest the claimed limitations. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897 /JORGE ANDRES LOPEZ/Examiner, Art Unit 2897
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Prosecution Timeline

Nov 16, 2023
Application Filed
Aug 06, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
99%
With Interview (+8.0%)
3y 5m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 33 resolved cases by this examiner. Grant probability derived from career allowance rate.

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