Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 11, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The Amendment filed November 25, 2025 has been entered. Claims 1-20 remain pending in the application. Claims 1, 5, 8, & 10-11 have been amended, and claims 15-20 are newly added. Applicant’s amendments to the and Claims are not aimed to overcome any objection or 35 U.S.C. § 112(b) rejections, none were previously set forth in the Non-Final Office Action mailed July 25, 2025, hereafter referred to as the Non-Final Office Action.
Response to Arguments
Applicant's arguments filed November 25, 2025 have been fully entered and considered but they are not persuasive. The applicant has presented a set of arguments pointing out their rationale of how the prior art references made of record in the most recent Office Action do not teach the currently recited claim limitations. Applicant in their submitted response has presented the argument that the primary reference, Betser et al. (US2008/0094127A1), and the secondary reference, Walter (US6438005B1), fail to disclose, teach, or suggest, individually or in combination, each and every limitation recited in amended independent claim 1, amended independent claims 5 & 11, and independent claim 9, recite similar elements to amended independent claim 1.
In response to applicant's arguments, please see pages 7-10 of applicant’s remarks, with respect to the rejection of claims 1, 5, 9, & 11, under U.S.C. § 103, that prior art references, Betser, in view of Walter, as cited by the applicant, fail to teach, disclose, or suggest individually or in combination, to show certain features of the invention: “measuring ,…an input current into a switched capacitor power conversion circuit, and calculating,… an estimated output current from the switched capacitor power conversion circuit as: IOUT = (IIN X N) -Offset, wherein IOUT is the estimated output current, IIN is the measured input current, N is a multiplication or division factor of the switched capacitor power conversion circuit, and Offset is an output current offset.”.
The examiner respectfully disagrees based on two reasonings, regarding the argument that Betser, in view of Walter, fail to teach, disclose or suggest individually or in combination, “measuring ,…an input current into a switched capacitor power conversion circuit, and calculating,… an estimated output current from the switched capacitor power conversion circuit as: IOUT = (IIN X N) -Offset, wherein IOUT is the estimated output current, IIN is the measured input current, N is a multiplication or division factor of the switched capacitor power conversion circuit, and Offset is an output current offset.” The first reason, in regard to obviousness, upon review, the examiner’s rejection satisfies the requirements for applying Rationales (A), (B), (D), (E), (F), and (G) in 2143(I)(A), 2143(I)(B), 2143(I)(D), 2143(I)(E), and 2143(I)(G). Therefore, the arguments are not persuasive because the arguments do not meet the requirements of 37 C.F.R. 1.111(b), and upon review, the rejection effectively makes a case of obviousness and motivation to combine the prior art references using either Rationales A, B, D, E, and F.
The second reason is that prior art references, Betser, in view of Walter, as presented by the applicant, disclose, teach or suggest, “measuring,… and calculating,…an estimated output current… IOUT = (IIN X N) -Offset, …offset.”. Betser measures the input current (I1) flowing in the charge pump pipe ([Abstract], [0083], [0085]-[0086], [0131], [Claim 1], [Claim 16], & [Claim 17]), using a microcontroller (hardware processor) to receive signals and perform control/calculations ([0097] &[0161]), further teaching the base calculation Iout = IIN (Eq. 5) ([0121]-[0130]), Walter teaches varying the ratio N between input and output ([Col. 2, ll. 13-19] & [Col. 4, ll. 34-40 & 56-67]), where the combination incorporates multiplying the input of the mode factor N and subtracting the known losses (Offset), and further teaching the different parameters of the equation (i.e., estimated output current (Iout), measured input current (IIN)) in Betser ([0083], [0085]-[0086], [0101], [0148], [0161], [0166]-[0167], [Claim 1], [Claim 2], [Claim 10], [Claim 16], [Claim 17], [Claim 18]), and both prior art references recognize non-ideal current losses (offsets), Betser “I2 = I1 + I_parasitic” ([0125]-[0130]) and Walter ([Col. 2, ll. 13-19]). Further disclosed in the Non-Final OA Pgs. 3-6, where the paragraphs and figures disclose all the features of the claimed invention.
In response to the applicant’s arguments, with respect to the rejection of amended independent claims 1, 5, & 11, & independent claim 9, under U.S.C. § 103, that prior art references, Betser, in view of Walter, as cited by the applicant, fail to teach, disclose, or suggest individually or in combination, stating the prior art references “cannot be combined”, to show certain features of the invention because “there is no motivation to combine the references” and because “the combination would be inoperable…”.
The examiner respectfully disagrees based on two reasonings, regarding the argument that Betser, in view of Walter, fail to teach, disclose or suggest individually or in combination, stating the prior art references “cannot be combined”, to show certain features of the invention because “there is no motivation to combine the references” and because “the combination would be inoperable…”. The first reason, in regard to motivation, upon review, the examiner’s rejection satisfied the requirements for applying Rationales (A), (B), (D), (E), (F), and (G) in 2143(I)(A), 2143(I)(B), 2143(I)(D), 2143(I)(E), and 2143(I)(G). Therefore, the arguments are not persuasive because the arguments do not meet the requirements of 37 C.F.R. 1.111(b), and upon review, the rejection effectively makes a case of obviousness and motivation to combine the prior art references using either Rationales A, B, D, E, and F.
The second reasoning, in response to applicant’s argument that there is no teaching, suggestion or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, incorporating the multiplication factor N taught by Walter ([Col. 2, ll. 13-19] & [Col. 4, ll. 34-40 & 56-67]) to accommodate different operating modes (i.e., 3-to-2 or 2-to-1) and subtracting the parasitic losses (Offset), recognized by both Betser ([0126]-[0130]) and Walter, achieve the accurate value of the current consumption desired by Betser ([0166]-[0167]).
In response to the applicant’s arguments, with respect to the rejection of the amended independent claims 1, 5, & 11, and independent claim 9, under U.S.C. § 103, that the prior art reference, Betser, as cited by the applicant, fails to teach, disclose, or suggest individually, to show certain features of the invention, an “offset”, as understood by those of skill in the art.
The examiner respectfully disagrees based on two reasonings, regarding the argument that Betser, as cited by the applicant, fails to teach, disclose or suggest individually, an “offset”, as understood by those of skill in the art. The first reason, applicant’s argument against references individually, discussed in MPEP § 2145(IV), nonobviousness cannot be demonstrated by critiquing prior art references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).Applicant’s reply fails to address the combined teaching of the applied references and instead argues that a prior art reference, individually, does not teach, disclose, or suggest all of the claim limitations. All of the limitations of the claim are disclosed in combination of Betser, in view of Walter, and it is the combination of the references that renders the claimed invention obvious.
The second reasoning is that the technical content of the prior art references, is either explicitly or inherently asserted (MPEP 2112 (III)) and upon review, the examiner’s rejection satisfied the requirements for applying Rationale A and B in 2143(I)(A) and 2143(I)(B). The argument is not persuasive because it does not meet the requirements of 37 C.F.R. 1.111(b), and, upon review, the rejection does make a prima facie case of obviousness, the requirements for a prima facie case of obviousness are discussed in MPEP 2143. Prior art references, Betser, in view of Walter, in combination, teach the “Offset” in the calculation, Betser teaches the fundamental relationship of the equation in Equations (4) and (5) ([0121]-[0130]), where “Iout = I1”, corresponding to the formula where the N=1 (multiplication or division factor), ([0126]-[0130] & [0161]). Walter is used to teach the N factor, disclosing a switched capacitor circuit that operates in various modes with different current ratios ([Col. 2, ll. 13-19] & [Col. 4, ll. 34-40 & 56-67]). The combination of prior art references would incorporate the multiplication/division factor N taught by Walter to accommodate different operating modes and subtracting the parasitic losses (Offset) recognized by Betser ([0166]-[0167]) and Walter ([Col. 2, ll. 13-19] & [Col. 4, ll. 34-40 & 56-67]).
Based on the reasons explained above, the applicant’s arguments are unconvincing. The examiner believes that the prior art references teach all the limitations currently recited in amended independent claims 1, 5, & 11, independent claim 9, to include dependent claims 2-4, 6-8, 10, & 12-20, which depend from and incorporate the limitations of amended independent claims 1, 5, & 11, & independent claim 9, therefore, the rejections are respectively maintained.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 15-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 15 recites “wherein a value of Offset is determined by measuring a difference between a measured current corresponding with IOUT and a measured current corresponding with IIN x N.”, in ll. 1-3, where the claim limitations are not previously disclosed, present in the disclosure or drawings, or disclosed in the paragraphs indicated by the applicant’s remarks, pgs. 7-10, and a POSITA would not take the measurements described, unless explicitly described in the disclosures provided.
Claim 16 recites “wherein a value of Offset is programmed in a memory circuit for subsequent access.”, in ll. 1-2, where the claim limitations are not previously disclosed, present in the disclosure or drawings, or disclosed in the paragraphs indicated by the applicant’s remarks, Pgs. 7-10, and a POSITA would not specifically store the Offset value in a memory circuit, as other forms of memory exist, unless explicitly described in the disclosures provided.
Claim 17 recites “wherein the input current is received from a DC input voltage supply.”, in ll. 1-2, where the claim limitations are not previously disclosed, present in the disclosure or drawings, or disclosed in the paragraphs indicated by the applicant’s remarks, Pgs. 7-10, and a POSITA would have different options for a DC input voltage supply, as other forms of DC input voltage supply exist and available to incorporate, unless explicitly described in the disclosures provided. Claims 18-20 are rejected by virtue of dependency on claim 17, which does not rectify the defect.
Claim 18 recites “wherein the switched capacitor power conversion circuit is configured to provide a voltage conversion between a voltage of the DC input voltage supply and an output voltage node.”, in ll. 1-3, where the claim limitations are not previously disclosed, present in the disclosure or drawings, or disclosed in the paragraphs indicated by the applicant’s remarks, Pgs. 7-10, and a POSITA would have not be aware of the voltage conversion and the specific output voltage node, since claim 18 depends from claim 17, as different forms of DC input voltage supply exist and available to incorporate, therefore multiple output voltage nodes could be present, unless explicitly described in the disclosures provided. Claims 19-20 are rejected by virtue of dependency on claim 18, which does not rectify the defect.
Claim 19 recites “wherein the switched capacitor power conversion circuit is configured to provide the output current to the output voltage to the output voltage node.”, in ll. 1-2, where the claim limitations are not previously disclosed, present in the disclosure or drawings, or disclosed in the paragraphs indicated by the applicant’s remarks, Pgs. 7-10, and a POSITA would have not be aware of the output current and the specific output voltage node, since claim 19 depends from claims 17-18, different forms of DC input voltage supply exist and available to incorporate, therefore multiple output voltage nodes with different output currents could be present, unless explicitly described in the disclosures provided. Claims 19-20 are rejected by virtue of dependency on claim 18, which does not rectify the defect.
Claim 20 recites “wherein a value of Offset is programmed in a memory circuit for subsequent access.”, in ll. 1-2, where the claim limitations are not previously disclosed, present in the disclosure or drawings, or disclosed in the paragraphs indicated by the applicant’s remarks, Pgs. 7-10, and a POSITA would not specifically store the Offset value in a memory circuit, as other forms of memory exist, unless explicitly described in the disclosures provided.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation "a first output current offset for the switched capacitor power conversion circuit using the equation:" in ll. 7-8, and “and Offset is the first output current offset”, in ll. 11-12, without prior disclosure. There is insufficient antecedent basis for “the equation” and “the first output current offset” limitations in the claim. For examination purposes, the examiner interprets these claim limitations as “a first output current offset for the switched capacitor power conversion circuit using equation:” and “and Offset is a first output current offset”. Claims 12-14 are rejected by virtue of dependency on claim 11, which do not rectify the defect.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 & 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Betser et al. (US 2008/0094127 A1, Pub. Date Apr. 24, 2008, hereinafter de Betser), in view of Walter (US 6438005 B1, Pat. Date Aug. 20, 2002, hereinafter Walter).
Regarding independent claim 1, Betser, teaches:
A method for estimating an output current of a charge pump ([Title], [Abstract], [0083], [0097], & [0130]-[0132]), the method comprising ([0083]): measuring, using a first sensing circuit ([0130]-[0131] & [0148]: measures the input current I1 flowing into the charge pump (switched capacitor circuit)), an input current into a switched capacitor power conversion circuit (Fig. 1A; [0085], [0118], [0130]-[0132], [0148], [0161] & [Claim 1]: the switched capacitor power conversion circuit is the “Conventional Control Circuit” in the charge pump); and
calculating, using a hardware processor, an estimated output current from the switched capacitor power conversion circuit as ([0092], [0097], [0118]-[0119], [0121], [0130]-[0132], [0140], & [0161]: teaches using the measured input current to determine the output current, which requires a calculation by a processor (Control Circuit or “hardware processor”), to receive signals and calculate the output current, the switched capacitor power conversion circuit is the “Conventional Control Circuit” in the charge pump):
IOUT = (IIN x N) – Offset ([0121]-[0130]: discloses this calculation where N = 1 and Offset = 0 (ideal case) or accounting for parasitic error, N is also discussed as a number of stages, establishing the variable nature of the circuit parameters)
wherein IOUT is the estimated output current (Fig. 2A; [0014], [0086], [0101], [0122]-[0123] & [0130]-[0132]: teaches the relationship “IOUT = IIN – Offset”, Betser’s equation teaches “Icp_in = I1 + N*I2”, where Icp_in is total IIN, I1 is IOUT, “Based on equation (5), the charge pump’s output current (IOUT) can be measured by measuring the input current (I1) of the charge pump’s pipe. (Typically the charge pump’s output current (IOUT) would be measured from the output, but according to a technique of an embodiment of this disclosure, IOUT can be measured from the input as well)” or estimating IOUT, and N*I2 is the Offset, further teaching subtracting an offset, and Icp_in is the total input current, which is the sum of the current delivered to the output I1 and the current consumed by the internal stage drivers N*I2), IIN is the measured input current (Fig. 2A; [0014], [0099]-[0100], [0121]-[0123], [0125]-[0132], [0148], & [0166]-[0167]: teaches the relationship “IOUT = IIN – Offset”, Betser’s equation “Icp_in = I1 + N*I2”, where Icp_in is total IIN), and Offset is an output current offset (Fig. 2A; [0014], [0121]-[0123], [0125]-[0132], & [0166]-[0167]: teaches the relationship “IOUT = IIN – Offset”, Betser’s equation “Icp_in = I1 + N*I2”, where N*I2 is the Offset and acknowledges offsets (parasitic current/errors) that affect the calculation accuracy (i.e., I2 = I1 + I_parasitic), a zero offset would fall within range).
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Betser, is silent in regard to:
N is a multiplication or division factor of the switched capacitor power conversion circuit,
However, Walter, further teaches:
N is a multiplication or division factor of the switched capacitor power conversion circuit ([Col. 2, ll. 13-19 & 43-49] & [Col. 4, ll. 34-40 & 56-67]: teaches the relationship N, multiple modes with different conversion factors, where a switched capacitor is operable in a plurality of modes, such as “operates in a “3-to-2” mode wherein the average input current is approximately two-thirds (2/3) the average output current”, rearranging the formula to IOUT = IIN * 1.5, or 1-to-1 mode, or 2-to-1 mode),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the calculation in Betser, which estimates the output current based on input current, by incorporating the multiplication or division factor, N, of the switched capacitor power conversion circuit, taught by Walter, in order to accommodate different operating modes (1-to-1, 2-to-1, or 3-to-2) and subtracting the parasitic losses (Offset) that is recognized by Betser and Walter, to achieve the accurate value of current consumption desired by Betser ([0166] & [0170]-[0171]), improving the accuracy by incorporating the Offset term taught by Betser to account for losses, and yielding predictable results (calculation formula IOUT = (IIN x N) – Offset) (KSR).
Regarding dependent claim 2, Betser, teaches:
The method of claim 1 ([Title], [Abstract], [0083], [0097], & [0130]-[0132]), wherein the hardware processor is configured to execute computer-readable instructions to calculate the estimated output current from the switched capacitor power conversion circuit (Figs. 2A & 2B; [0008], [0011] [0096]-[0097], [0118]-[0119], [0121], [0131]-[0132], [0140]-[0148], [0161], & [0170]: discloses a “Control Circuit” which is a hardware processor that performs the control functions with a “program” in the flash memory cells, containing “computer-readable instructions” using the measured input current to determine the estimated output current from the switched capacitor power conversion circuit (Conventional Control Circuit in the charge pump), which requires a calculation by a processor).
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Regarding dependent claim 3, Betser, teaches:
The method of claim 1 ([Title], [Abstract], [0083], [0097], & [0130]-[0132]), wherein the hardware processor comprises an integrated circuit configured to calculate the estimated output current from the switched capacitor power conversion circuit (Figs. 2A & 2B; [Abstract], [0008], [0011] [0096]-[0097], [0118]-[0119], [0121], [0131]-[0132], [0140]-[0148], [0161], [0170], & [Claim 12]: discloses a “Control Circuit” which is a hardware processor that performs the control functions with a “program” in the flash memory cells, containing “computer-readable instructions” using the measured input current to determine the estimated output current from the switched capacitor power conversion circuit (Conventional Control Circuit in the charge pump), which requires a calculation by a processor, and teaches that the entire system can be implemented on an “integrated circuit (IC) chip”).
Regarding dependent claim 4, Betser, teaches:
The method of claim 1 ([Title], [Abstract], [0083], [0097], & [0130]-[0132]), further comprising:
Betser, is silent in regard to:
measuring, using a second sensing circuit, an input voltage into a switched capacitor power conversion circuit;
wherein the output current offset is determined based on the measured input voltage.
However, Walter, further teaches:
measuring, using a second sensing circuit (Fig. 3; [Col. 5, ll. 43-47]: “Switch/mode control circuitry 20 includes resistors 50a-50c and comparators 52a and 52b.” where the comparators (52a and 52b) along with the resistors are the first (comparator 52a) and second (comparator 52b) sensing circuits), an input voltage into a switched capacitor power conversion circuit (Figs. 1 & 3; [Col. 2, ll. 43-49 & 66-67], [Col. 3, ll. 1], [Col. 5, ll. 27-40, 43-47, & 50-53] & [Col. 6, ll. 1-3]: teaches measuring the input voltage (12 (VIN)) to select the mode of operation);
wherein the output current offset is determined based on the measured input voltage ([Col. 2, ll. 13-19 & 40-49], [Col. 4, ll. 34-40 & 56-65], [Col. 5, ll. 43-54], & [Col. 6, ll. 1-3]: teaches measuring input voltage for control purposes, and inherently obvious to make the offset term a function of the input voltage rather than a fixed constant, and using this existing measurement to adjust the Offset value, Offset value being the “losses” and “quiescent current losses in the control circuitry of the regulator, switch losses, switch driver current losses”).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate measuring, using a second sensing circuit, an input voltage into a switched capacitor power conversion circuit, where the output current offset is determined based on the measured input voltage, of Walter to Betser, in order to attain Betser’s estimation method, determining the output current of a charge pump by measuring the input voltage and accounting for an offset, and combining with Walter’s teachings, various charge pump configurations with different current conversion ratios (N) and measuring input voltage for control, then creating the accurate estimation method, by taking Walter’s formula, updating it with the offset term from Betser, and further refining the offset term by making it a function of the measured input voltage from Walter’s method for improved accuracy, and yielding predictable results (KSR).
Regarding independent claim 5, Betser, teaches:
An apparatus for estimating an output current of a charge pump (Fig. 2A; [Title], [Abstract], [0083], [0085]-[0086], [0097], [0130]-[0132], & [Claim 17]), the apparatus comprising ([Abstract], [0083], & [0085]-[0086]):
a first sensing circuit is configured to measure an input current into a switched capacitor power conversion circuit (Figs. 1A & 2A; [0085], [0118]-[0119], [0130]-[0132], [0148], [0161], [Claim 1], & [Claim 17]: teaches an apparatus with a “means for measuring a first current (I1) coming into the charge pump”, where the charge pump is a sensing circuit and the “Conventional Control Circuit” is the switched capacitor power conversion circuit in the charge pump); and
a hardware processor is configured to calculate an estimated output current from the switched capacitor power conversion circuit as ([0092], [0097], [0118]-[0119], [0121], [0130]-[0132], [0140], & [0161]: teaches a “Control Circuit” which is a hardware processor that uses the measured input current to determine the output current from the “Conventional Control Circuit”, is the switched capacitor power conversion circuit):
IOUT = (IIN x N) - Offset ([0121]-[0130]: discloses this calculation where N = 1 and Offset = 0 (ideal case) or accounting for parasitic error, N is also discussed as a number of stages, establishing the variable nature of the circuit parameters)
wherein IOUT is the estimated output current (Fig. 2A; [0014], [0086], [0101], [0122]-[0123] & [0130]-[0132]: teaches the relationship “IOUT = IIN – Offset”, Betser’s equation teaches “Icp_in = I1 + N*I2”, where Icp_in is IIN, I1 is IOUT, “Based on equation (5), the charge pump’s output current (IOUT) can be measured by measuring the input current (I1) of the charge pump’s pipe. (Typically the charge pump’s output current (IOUT) would be measured from the output, but according to a technique of an embodiment of this disclosure, IOUT can be measured from the input as well)” or estimating IOUT, and N*I2 is the Offset, further teaching subtracting an offset, Icp_in is the total input current, which is the sum of the current delivered to the output I1 and the current consumed by the internal stage drivers N*I2), IIN is the measured input current (Fig. 2A; [0014], [0099]-[0100], [0121]-[0123], [0125]-[0132], [0148], & [0166]-[0167]: teaches the relationship “IOUT = IIN – Offset”, Betser’s equation “Icp_in = I1 + N*I2”, where Icp_in is total IIN), and Offset is an output current offset (Fig. 2A; [0014], [0121]-[0123], [0125]-[0132], & [0166]-[0167]: Betser teaches the relationship “IOUT = IIN – Offset”, Betser’s equation “Icp_in = I1 + N*I2”, where N*I2 is the Offset and acknowledges offsets (parasitic current/errors) that affect the calculation accuracy (i.e., I2 = I1 + I_parasitic), a zero offset would fall within range).
Betser, is silent in regard to:
N is a multiplication or division factor of the switched capacitor power conversion circuit,
However, Walter, further teaches:
N is a multiplication or division factor of the switched capacitor power conversion circuit ([Col. 2, ll. 13-19 & 43-49] & [Col. 4, ll. 34-40 & 56-67]: teaches the relationship N, multiple modes with different conversion factors, where a switched capacitor is operable in a plurality of modes, such as “operates in a “3-to-2” mode wherein the average input current is approximately two-thirds (2/3) the average output current”, rearranging the formula to IOUT = IIN * 1.5, or 1-to-1 mode, or 2-to-1 mode),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the calculation in Betser, which estimates the output current based on input current, by incorporating the multiplication or division factor, N, of the switched capacitor power conversion circuit, taught by Walter, in order to accommodate different operating modes (1-to-1, 2-to-1, or 3-to-2) and subtracting the parasitic losses (Offset) that is recognized by Betser and Walter, to achieve the accurate value of current consumption desired by Betser ([0166] & [0170]-[0171]), improving the accuracy by incorporating the Offset term taught by Betser to account for losses, and yielding predictable results (calculation formula IOUT = (IIN x N) – Offset) (KSR).
Regarding dependent claim 6, Betser, teaches:
The apparatus of claim 5 (Fig. 2A; [Title], [Abstract], [0083], [0085]-[0086], [0097], [0130]-[0132], & [Claim 17]), wherein the hardware processor is configured to execute computer-readable instructions to calculate the estimated output current from the switched capacitor power conversion circuit (Figs. 2A & 2B; [0008], [0011] [0096]-[0097], [0118]-[0119], [0121], [0131]-[0132], [0140]-[0148], [0161], & [0170]: discloses a “Control Circuit” which is a hardware processor that performs the control functions with a “program” in the flash memory cells, containing “computer-readable instructions” using the measured input current to determine the estimated output current from the switched capacitor power conversion circuit (Conventional Control Circuit in the charge pump), which requires a calculation by a processor).
Regarding dependent claim 7, Betser, teaches:
The apparatus of claim 5 (Fig. 2A; [Title], [Abstract], [0083], [0085]-[0086], [0097], [0130]-[0132], & [Claim 17]), wherein the hardware processor comprises an integrated circuit configured to calculate the estimated output current from the switched capacitor power conversion circuit (Figs. 2A & 2B; [Abstract], [0008], [0011] [0096]-[0097], [0118]-[0119], [0121], [0131]-[0132], [0140]-[0148], [0161], [0170], [Claim 12], & [Claim 17]: discloses a “Control Circuit” which is a hardware processor that performs the control functions with a “program” in the flash memory cells, containing “computer-readable instructions” using the measured input current to determine the estimated output current from the switched capacitor power conversion circuit (Conventional Control Circuit in the charge pump), which requires a calculation by a processor, and teaches that the entire system can be implemented on an “integrated circuit (IC) chip”).
Regarding dependent claim 8, Betser, teaches:
The apparatus of claim 5 (Fig. 2A; [Title], [Abstract], [0083], [0085]-[0086], [0097], [0130]-[0132], & [Claim 17]), further comprising:
Betser, is silent in regard to:
a second sensing circuit is configured to measure an input voltage into a switched capacitor power conversion circuit;
wherein the output current offset is determined based on the measured input voltage.
However, Walter, further teaches:
a second sensing circuit is configured to measure (Fig. 3; [Col. 5, ll. 43-47]: “Switch/mode control circuitry 20 includes resistors 50a-50c and comparators 52a and 52b.” where the comparators (52a and 52b) along with the resistors are the first (comparator 52a) and second (comparator 52b) sensing circuits) an input voltage into a switched capacitor power conversion circuit (Figs. 1 & 3; [Col. 2, ll. 43-49 & 66-67], [Col. 3, ll. 1], [Col. 5, ll. 27-40, 43-47, & 50-53] & [Col. 6, ll. 1-3]: teaches measuring the input voltage (12 (VIN)) to select the mode of operation);
wherein the output current offset is determined based on the measured input voltage ([Col. 2, ll. 13-19 & 40-49], [Col. 4, ll. 34-40 & 56-65], [Col. 5, ll. 43-54], & [Col. 6, ll. 1-3]: teaches measuring input voltage for control purposes, and inherently obvious to make the offset term a function of the input voltage rather than a fixed constant, and using this existing measurement to adjust the Offset value, Offset value being the “losses” and “quiescent current losses in the control circuitry of the regulator, switch losses, switch driver current losses”).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a second sensing circuit to measure an input voltage into a switched capacitor power conversion circuit, where the output current offset is determined based on the measured input voltage, of Walter to Betser, in order to attain Betser’s estimation apparatus, determining the output current of a charge pump by measuring the input current and accounting for an offset, and combining with Walter’s apparatus teachings, includes a circuit for measuring the input voltage for control and various charge pump configurations with different current conversion ratios (N), to create the accurate estimation apparatus, by taking Walter’s formula, updating it with the offset term from Betser, and further refining the offset term by making it a function of the measured input voltage from Walter’s apparatus for improved accuracy, and yielding predictable results (KSR).
Regarding independent claim 9, Betser, teaches:
A computer-readable medium storing processor-executable instructions for estimating an output current of a charge pump (Figs. 2A & 2B; [Title], [Abstract], [0008], [0011], [0083], [0085]-[0086], [0096]-[0097], [0118]-[0119], [0121], [0130]-[0132], [0140]-[0148], [0161], & [0170]: discloses a “Control Circuit” which is a processor that performs the control functions with a “program” in the flash memory cells (computer-readable medium), containing/storing “processor-executable instructions” using the measured input current to determine the estimated output current from the switched capacitor power conversion circuit (Conventional Control Circuit in the charge pump), which requires a calculation by a processor), the processor-executable instructions comprising instructions to ( Fig. 2A; [Abstract], [0008], [0096]-[0097], [0121], [0130]-[0132], [0140]-[0148], [0161], & [0170]: discloses a “Control Circuit” which is a processor that performs the control functions with a “program” in the flash memory cells (computer-readable medium), containing “processor-executable instructions”):
calculate an estimated output current from a switched capacitor power conversion circuit as ([0092], [0097], [0118]-[0119], [0121], [0130]-[0132], [0140], & [0161]: teaches using the measured input current to determine the output current, which requires a calculation by a processor (Control Circuit or “hardware processor”), the switched capacitor power conversion circuit is the “Conventional Control Circuit” in the charge pump):
IOUT = (IIN x N) - Offset ([0121]-[0130]: discloses this calculation where N = 1 and Offset = 0 (ideal case) or accounting for parasitic error, N is also discussed as a number of stages, establishing the variable nature of the circuit parameters)
wherein IOUT is the estimated output current (Fig. 2A; [0014], [0086], [0101], [0122]-[0123] & [0130]-[0132]: teaches the relationship “IOUT = IIN – Offset”, Betser’s equation teaches “Icp_in = I1 + N*I2”, where Icp_in is IIN, I1 is IOUT, “Based on equation (5), the charge pump’s output current (IOUT) can be measured by measuring the input current (I1) of the charge pump’s pipe. (Typically the charge pump’s output current (IOUT) would be measured from the output, but according to a technique of an embodiment of this disclosure, IOUT can be measured from the input as well)” or estimating IOUT, and N*I2 is the Offset, further teaching subtracting an offset, Icp_in is the total input current, which is the sum of the current delivered to the output I1 and the current consumed by the internal stage drivers N*I2), IIN is an input current into the switched capacitor power conversion circuit that is measured using a first sensing circuit (Fig. 2A; [0014], [0099]-[0100], [0118]-[0119], [0121]-[0123], [0125]-[0132], [0148], [0166]-[0167], & [Claim 1]: teaches the relationship “IOUT = IIN – Offset”, Betser’s equation “Icp_in = I1 + N*I2”, where Icp_in is total IIN, instructions would operate on value of IIN (Icp_in) measured, and the switched capacitor power conversion circuit is the “Conventional Control Circuit” in the charge pump), and Offset is an output current offset (Fig. 2A; [0014], [0121]-[0123], [0125]-[0132], & [0166]-[0167]: Betser teaches the relationship “IOUT = IIN – Offset”, Betser’s equation “Icp_in = I1 + N*I2”, where N*I2 is the Offset and acknowledges offsets (parasitic current/errors) that affect the calculation accuracy (i.e., I2 = I1 + I_parasitic), a zero offset would fall within range).
Betser, is silent in regard to:
N is a multiplication or division factor of the switched capacitor power conversion circuit,
However, Walter, further teaches:
N is a multiplication or division factor of the switched capacitor power conversion circuit ([Col. 2, ll. 13-19 & 43-49] & [Col. 4, ll. 34-40 & 56-67]: teaches the relationship N, multiple modes with different conversion factors, where a switched capacitor is operable in a plurality of modes, such as “operates in a “3-to-2” mode wherein the average input current is approximately two-thirds (2/3) the average output current”, rearranging the formula to IOUT = IIN * 1.5, or 1-to-1 mode, or 2-to-1 mode),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the calculation in Betser, which estimates the output current based on input current, by incorporating the multiplication or division factor, N, of the switched capacitor power conversion circuit, taught by Walter, in order to accommodate different operating modes (1-to-1, 2-to-1, or 3-to-2) and subtracting the parasitic losses (Offset) that is recognized by Betser and Walter, to achieve the accurate value of current consumption desired by Betser ([0166] & [0170]-[0171]), improving the accuracy by incorporating the Offset term taught by Betser to account for losses, and yielding predictable results (calculation formula IOUT = (IIN x N) – Offset) (KSR).
Regarding dependent claim 10, Betser, teaches:
The computer-readable medium of claim 9 (Figs. 2A & 2B; [Title], [Abstract], [0008], [0011], [0083], [0085]-[0086], [0096]-[0097], [0118]-[0119], [0121], [0130]-[0132], [0140]-[0148], [0161], & [0170]),
Betser, is silent in regard to:
wherein the output current offset is determined based on an input voltage into the switched capacitor power conversion circuit that is measured using a second sensing circuit.
However, Walter, further teaches:
wherein the output current offset is determined based on an input voltage (Figs. 1 & 3; [Col. 2, ll. 43-49 & 66-67], [Col. 3, ll. 1], [Col. 4, ll. 56-65], [Col. 5, ll. 27-40, 43-47, & 50-53] & [Col. 6, ll. 1-3]: teaches measuring the input voltage (12 (VIN)) to select the mode of operation) into the switched capacitor power conversion circuit ([Col. 2, ll. 13-19 & 43-49], [Col. 5, ll. 43-54], & [Col. 6, ll. 1-3]: teaches input voltage for control purposes, and inherently obvious to make the offset term a function of the input voltage rather than a fixed constant, and using this existing measurement to adjust the Offset value, Offset value being the “losses” and “quiescent current losses in the control circuitry of the regulator, switch losses, switch driver current losses”) that is measured using a second sensing circuit (Fig. 3; [Col. 5, ll. 43-47]: “Switch/mode control circuitry 20 includes resistors 50a-50c and comparators 52a and 52b.” where the comparators (52a and 52b) along with the resistors are the first (comparator 52a) and second (comparator 52b) sensing circuits).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the output current offset based on an input voltage into the switched capacitor power conversion circuit, that is measuring using a second sensing circuit, of Walter to Betser, in order to attain an estimation medium to create a general set of instructions, instructing the processor to determine the output current of a charge pump by measuring the input voltage and accounting for an offset, to create the accurate estimation medium, by taking Walter’s formula, updating it with the offset term from Betser, and further refining the offset term by making it a function of the measured input voltage from Walter for improved accuracy, and yielding predictable results (KSR).
Regarding independent claim 11, Betser, teaches:
A method for one-time estimation of an output current offset for a charge pump ([Title], [Abstract], [0083], [0085]-[0086], [0097], & [0130]-[0132]), the method comprising ([0083]):
measuring, using a first sensing circuit ([0130]-[0131] & [0148]), an input current into a switched capacitor power conversion circuit (Fig. 1A; [0085], [0118]-[0119], [0130]-[0132], [0161] & [Claim 1]: switched capacitor power conversion circuit is the “Conventional Control Circuit” in the charge pump);
calculating, using a hardware processor, a first output current offset for the switched capacitor power conversion circuit using the equation (Figs. 2A & 2B; [0008], [0011], [0092], [0096]-[0097], [0118]-[0119], [0121], [0125]-[0132], [0140]-[0148], [0161], & [0170]: discloses a “Control Circuit” which is a hardware processor that performs the control functions with a “program” in the flash memory cells, containing “computer-readable instructions” using a first measured input current to determine the estimated output current from the switched capacitor power conversion circuit (Conventional Control Circuit in the charge pump), which requires a calculation by a processor):
IOUT = (IIN x N) - Offset ([0121]-[0130]: discloses this calculation where N = 1 and Offset = 0 (ideal case) or accounting for parasitic error, N is also discussed as a number of stages, establishing the variable nature of the circuit parameters)
wherein IOUT is the measured output current (Fig. 2A; [0014], [0086], [0101], [0122]-[0123] & [0130]-[0132]: teaches the relationship “IOUT = IIN – Offset”, Betser’s equation teaches “Icp_in = I1 + N*I2”, where Icp_in is IIN, I1 is IOUT, “Based on equation (5), the charge pump’s output current (IOUT) can be measured by measuring the input current (I1) of the charge pump’s pipe. (Typically the charge pump’s output current (IOUT) would be measured from the output, but according to a technique of an embodiment of this disclosure, IOUT can be measured from the input as well.)” or estimating IOUT, and N*I2 is the Offset, further teaching subtracting an offset, Icp_in is the total input current, which is the sum of the current delivered to the output I1 and the current consumed by the internal stage drivers N*I2), IIN is the measured input current (Fig. 2A; [0014], [0099]-[0100], [0118]-[0119], [0121]-[0123], [0125]-[0132], [0148], [0166]-[0167], & [Claim 1]: teaches the relationship “IOUT = IIN – Offset”, Betser’s equation “Icp_in = I1 + N*I2”, where Icp_in is total IIN, processor would operate on value of IIN (Icp_in) measured), and Offset is the first output current offset (Fig. 2A; [0014], [0121]-[0123], [0125]-[0132], & [0166]-[0167]: teaches the relationship “IOUT = IIN – Offset”, Betser’s equation “Icp_in = I1 + N*I2”, where N*I2 is the Offset of the first output current and acknowledges offsets (parasitic current/errors) that affect the calculation accuracy (i.e., I2 = I1 + I_parasitic), a zero offset would fall within range).
Betser, is silent in regard to:
measuring, using a second sensing circuit, an output current from the switched capacitor power conversion circuit;
N is a multiplication or division factor of the switched capacitor power conversion circuit,
However, Walter, further teaches:
measuring, using a second sensing circuit (Fig. 3; [Col. 5, ll. 43-47]: “Switch/mode control circuitry 20 includes resistors 50a-50c and comparators 52a and 52b.” where the comparators (52a and 52b) along with the resistors are the first (comparator 52a) and second (comparator 52b) sensing circuits), an output current from the switched capacitor power conversion circuit (Figs. 1 & 3; [Col. 2, ll. 13-19, 40-49, & 66-67], [Col. 3, ll. 1], [Col. 4, ll. 56-65], [Col. 5, ll. 1-21, 27-40, 43-53] & [Col. 6, ll. 1-3]: teaches measuring “output current load”, which is proportional to voltage signal inputs, to select the mode of operation);
N is a multiplication or division factor of the switched capacitor power conversion circuit ([Col. 2, ll. 13-19 & 43-49] & [Col. 4, ll. 34-40 & 56-67]: teaches the relationship N, multiple modes with different conversion factors, where a switched capacitor is operable in a plurality of modes, such as “operates in a “3-to-2” mode wherein the average input current is approximately two-thirds (2/3) the average output current”, rearranging the formula to IOUT = IIN * 1.5, or 1-to-1 mode, or 2-to-1 mode),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the calculation in Betser, which estimates the output current based on input current, by incorporating the second sensing circuit measuring an output current, and a multiplication or division factor, N, both from the switched capacitor power conversion circuit, taught by Walter, in order to attain a one-time estimation method, using the input and output current for various charge pump ratios (N) to accommodate different operating modes (1-to-1, 2-to-1, or 3-to-2) as taught by Walter, taking the relationship from Walter, N, measuring IIN and IOUT (as taught by Betser), and subtracting parasitic losses (Offset) that is recognized by Betser and Walter, to achieve the accurate value of current consumption desired by Betser ([0166] & [0170]-[0171]), improving the accuracy by incorporating and instructing the hardware processor to solve the combined equation to obtain the one-time estimation of the Offset as taught by Betser to account for losses, and yielding predictable results (KSR).
Regarding dependent claim 12, Betser, teaches:
The method of claim 11 ([Title], [Abstract], [0083], [0085]-[0086], [0097], & [0130]-[0132]), further comprising:
calculating, using the hardware processor (Figs. 2A & 2B; [0008], [0011], [0092], [0096]-[0097], [0118]-[0119], [0121], [0130]-[0132], [0140]-[0148], [0161], & [0170]: discloses a “Control Circuit” which is a hardware processor that performs the control functions with a “program” in the flash memory cells, containing “computer-readable instructions” using a first measured input current to determine the estimated output current from the switched capacitor power conversion circuit (Conventional Control Circuit in the charge pump), which requires a calculation by a processor),
Betser, is silent in regard to:
a second output current offset for the switched capacitor power conversion circuit by averaging the first output current offset across a range of the measured input current.
However, Walter, further teaches:
a second output current offset for the switched capacitor power conversion circuit (Figs. 1 & 3; [Abstract], [Col. 2, ll. 13-19, 40-49, & 66-67], [Col. 3, ll. 1], [Col. 4, ll. 37-40 & 56-65], [Col. 5, ll. 1-21, 27-40, 43-53] & [Col. 6, ll. 1-3]: teaches measuring “output current load”, which is proportional to voltage signal inputs, to select the mode of operation and measuring input voltage for control purposes, and inherently obvious to make the offset term a function of the input voltage rather than a fixed constant, and using this existing measurement to adjust the second output current Offset value(s), Offset value being the “losses” and “quiescent current losses in the control circuitry of the regulator, switch losses, switch driver current losses”, and teaches “a plurality of modes that match the power transferred by the switched capacitors to the power drawn by a load. Advantageously, the circuit and method increase the efficiency of the regulator circuit over varying input voltage levels and output current levels”) by averaging the first output current offset across a range of the measured input current ([Abstract], [Col. 1, ll. 5-8], [Col. 2, ll. 40-49], [Col. 4, ll. 37-40 & 56-65] [Col. 5, ll. 27-40]: teaches the “first output current offset” calculation at multiple points across the converter’s expected operating range, “over broad current ranges”, designed to operate over a range of input voltages and output currents, where averaging is a fundamental and universally known technique to reduce measurement noise and find a representative value for a parameter that can exhibit variations).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a second output current offset for the switched capacitor power conversion circuit by averaging the first output current offset across a range of the measured input current, of Walter to Betser, in order to attain and improve a one-time estimation method, measuring several points across the operational range and average the results (averaging is a fundamental and universal known technique to reduce measurement noise when searching for a representative value for a parameter that can exhibit variations), for the set of second offsets and averaging the first output current offset, by measuring the input and output current for various charge pump ratios (N) as taught by Walter, taking the relationship from Walter, N, measuring IIN and IOUT (as taught by Betser), incorporating Betser’s equations, increasing the accuracy by incorporating and instructing the hardware processor to solve the combined equation to obtain the one-time estimation (averaging a set of second output current Offsets) of the Offset as taught by Betser to account for losses, and yielding predictable results (KSR).
Regarding dependent claim 13, Betser, teaches:
The method of claim 12 ([Title], [Abstract], [0083], [0085]-[0086], [0097], & [0130]-[0132]), further comprising:
calculating, using the hardware processor (Figs. 2A & 2B; [0008], [0011], [0092], [0096], [0118]-[0119], [0121], [0130]-[0132], [0140]-[0147], [0161], & [0170]: discloses a “Control Circuit” which is a hardware processor that performs the control functions with a “program” in the flash memory cells, containing “computer-readable instructions” using a first measured input current to determine the estimated output current from the switched capacitor power conversion circuit (Conventional Control Circuit in the charge pump), which requires a calculation by a processor),
Betser, is silent in regard to:
a set of second output current offsets, each calculated second output current offset being calculated for a different input voltage; and
a third output current offset as an average of the set of second output current offsets.
However, Walter further teaches:
a set of second output current offsets, each calculated second output current offset being calculated for a different input voltage (Figs. 1 & 3; [Abstract], [Col. 2, ll. 13-19, 40-49, & 66-67], [Col. 3, ll. 1], [Col. 4, ll. 37-40 & 56-65], [Col. 5, ll. 1-21, 27-40, 43-53] & [Col. 6, ll. 1-3]: teaches measuring “output current load”, which is proportional to voltage signal inputs, to select the mode of operation and measuring input voltage for control purposes, and inherently obvious to make the offset term a function of the input voltage rather than a fixed constant, and using this existing measurement to adjust the second Offset value(s), Offset value being the “losses” and “quiescent current losses in the control circuitry of the regulator, switch losses, switch driver current losses”, and “a plurality of modes that match the power transferred by the switched capacitors to the power drawn by a load. Advantageously, the circuit and method increase the efficiency of the regulator circuit over varying input voltage levels and output current levels”); and
a third output current offset (Figs. 1 & 3; [Abstract], [Col. 2, ll. 13-19, 40-49, & 66-67], [Col. 3, ll. 1], [Col. 4, ll. 37-40 & 56-65], [Col. 5, ll. 1-21, 27-40, 43-53] & [Col. 6, ll. 1-3]: teaches measuring “output current load”, which is proportional to voltage signal inputs, to select the mode of operation and measuring input voltage for control purposes, and inherently obvious to make the offset term a function of the input voltage rather than a fixed constant, and using this existing measurement to adjust the third output current Offset value(s), Offset value being the “losses” and “quiescent current losses in the control circuitry of the regulator, switch losses, switch driver current losses”, and teaches “a plurality of modes that match the power transferred by the switched capacitors to the power drawn by a load. Advantageously, the circuit and method increase the efficiency of the regulator circuit over varying input voltage levels and output current levels”) as an average of the set of second output current offsets ([Abstract], [Col. 1, ll. 5-8], [Col. 2, ll. 40-49], [Col. 4, ll. 37-40 & 56-65], [Col. 5, ll. 27-40]: teaches the “second output current offset” calculation at multiple points across the converter’s expected operating range, “over broad current ranges”, designed to operate over a range of input voltages and output currents, where averaging is a fundamental and universally known technique to reduce measurement noise and find a representative value for a parameter that can exhibit variations).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a set of second output current offsets, each calculated for a different input voltage, and a third output current offset as an average of the set of second output current offsets, of Walter to Betser, in order to attain and improve a one-time estimation method, by repeating the measuring of several points across, such as the input voltages and the operational range, and average the results (averaging is a fundamental and universal known technique to reduce measurement noise and to obtain a representative value for a parameter that can exhibit variations), for the set of second offsets and repeating for the third output current offset, by measuring the input and output current for various charge pump ratios (N) as taught by Walter, taking the relationship from Walter, N, measuring IIN and IOUT (as taught by Betser), incorporating Betser’s equations, increasing the accuracy by incorporating and instructing the hardware processor to solve the combined equation to obtain the one-time estimation (averaging a third output current Offset) of the Offset as taught by Betser to account for losses, and yielding predictable results (KSR).
Regarding dependent claim 14, Betser, teaches:
The method of claim 12 ([Title], [Abstract], [0083], [0085]-[0086], [0097], & [0130]-[0132]), further comprising:
calculating, using the hardware processor (Figs. 2A & 2B; [0008], [0011], [0092], [0096], [0118]-[0119], [0121], [0130]-[0132], [0140]-[0147], [0161], & [0170]: discloses a “Control Circuit” which is a hardware processor that performs the control functions with a “program” in the flash memory cells, containing “computer-readable instructions” using a first measured input current to determine the estimated output current from the switched capacitor power conversion circuit (Conventional Control Circuit in the charge pump), which requires a calculation by a processor),
Betser, is silent in regard to:
a set of second output current offsets, each calculated second output current offset being calculated for a different input voltage; and
a set of third output current offsets, each third current offset corresponding to a different range of input voltage.
However, Walter, further teaches:
a set of second output current offsets, each calculated second output current offset being calculated for a different input voltage (Figs. 1 & 3; [Abstract], [Col. 2, ll. 13-19, 40-49, & 66-67], [Col. 3, ll. 1], [Col. 4, ll. 37-40 & 56-65], [Col. 5, ll. 1-21, 27-40, 43-53] & [Col. 6, ll. 1-3]: teaches measuring an “output current load”, which is proportional to different voltage signal inputs, to select the mode of operation and measuring input voltage for control purposes, and inherently obvious to make the offset term a function of the input voltage rather than a fixed constant, and using this existing measurement to adjust the set of second output current Offset values, Offset value being the “losses” and “quiescent current losses in the control circuitry of the regulator, switch losses, switch driver current losses”, and “a plurality of modes that match the power transferred by the switched capacitors to the power drawn by a load. Advantageously, the circuit and method increase the efficiency of the regulator circuit over varying input voltage levels and output current levels”); and
a set of third output current offsets (Figs. 1 & 3; [Abstract], [Col. 2, ll. 13-19, 40-49, & 66-67], [Col. 3, ll. 1], [Col. 4, ll. 37-40 & 56-65], [Col. 5, ll. 1-21, 27-40, 43-53] & [Col. 6, ll. 1-3]: teaches measuring an “output current load”, which is proportional to voltage signal inputs, to select the mode of operation and measuring input voltage for control purposes, and inherently obvious to make the offset term a function of the input voltage rather than a fixed constant, and using this existing measurement to adjust a set of third output current Offset values, Offset value being the “losses” and “quiescent current losses in the control circuitry of the regulator, switch losses, switch driver current losses”, and teaches “a plurality of modes that match the power transferred by the switched capacitors to the power drawn by a load. Advantageously, the circuit and method increase the efficiency of the regulator circuit over varying input voltage levels and output current levels”), each third current offset corresponding to a different range of input voltage ([Abstract], [Col. 2, ll. 13-19, 40-49, & 66-67], [Col. 3, ll. 1], [Col. 4, ll. 37-40 & 56-65], [Col. 5, ll. 1-21, 27-40, 43-53] & [Col. 6, ll. 1-3]: teaches “a plurality of modes that match the power transferred by the switched capacitors to the power drawn by a load. Advantageously, the circuit and method increase the efficiency of the regulator circuit over varying input voltage levels and output current levels” for each third current offset with “a different range of input voltage”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a set of second output current offsets, each calculated for a different input voltage, and a set of third output current offsets, each third current offset corresponding to a different range of input voltage, of Walter to Betser, in order to attain and improve a one-time estimation method, by repeating the measuring of several points across, such as the input voltages and the operational range, and average the results (averaging is a fundamental and universal known technique to reduce measurement noise and to obtain a representative value for a parameter that can exhibit variations), for the set of second offsets and repeating for the third set, by measuring the input and output current for various charge pump ratios (N) as taught by Walter, taking the relationship from Walter, N, measuring IIN and IOUT (as taught by Betser), incorporating Betser’s equations, increasing the accuracy by incorporating and instructing the hardware processor to solve the combined equation to obtain the one-time estimation (averaging a third output current Offset) of the Offset as taught by Betser to account for losses, and yielding predictable results (KSR).
Regarding dependent claim 17, Betser, teaches:
The method of claim 1 ([Title], [Abstract], [0011], [0083], [0097], & [0125]-[0132]), wherein the input current ([0006], [0011], [0121]-[0123], [0148], & [0166]-[0167])
Betser, is silent in regard to:
is received from a DC input voltage supply.
However, Walter, further teaches:
is received from a DC input voltage supply ([Title], [Col. 2, ll. 65-67], & [Col. 3, ll. 1-8]: discloses the input as a DC voltage source (battery) for a DC/DC converter).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the “supply voltage” in Betser is a DC input voltage supply, as charge pumps are inherently DC-to-DC converters designed to convert a DC source, such as a battery or supply taught by Walter, to another DC voltage level, this combination confirms the standard power source for this type of device, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
Regarding dependent claim 18, Betser, teaches:
The method of claim 17 ([Title], [Abstract], [0011], [0083], [0097], & [0125]-[0132]), wherein the switched capacitor power conversion circuit ([0003]-[0004]: describes a “charge pump (CP)” which is a switched capacitor conversion circuit) is configured to provide a voltage conversion ([0003]-[0004], [0006], & [0011]-[0013]: the core function of the Betser circuit is voltage conversion) between a voltage of the DC input voltage supply (Figs. 1A & 2A; [0006] & [0010]-[0013])
Betser, is silent in regard to:
and an output voltage node
However, Walter, further teaches:
and an output voltage node (Fig. 1; [Col. 2, ll. 1-2] & [Col. 3, ll. 1-8]: results provided at an output node, VOUT at terminal 14)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the switched capacitor power conversion circuit in Betser is “configured to provide a voltage conversion” between the input and output, with Walter reinforcing the DC input supply and the voltage conversion function in a switched capacitor, describing a switched capacitor converter that accepts an input voltage, VIN and provides a regulated DC output voltage VOUT, which is the fundamental purpose of a charge pump (to step up, step down, or invert voltage), the combination confirms that the circuit performs this standard function, as demonstrated by both prior art references, their combination both reinforces and yield predictable results (KSR).
Regarding dependent claim 19, Betser, teaches:
The method of claim 18 ([Title], [Abstract], [0011], [0083], [0097], & [0125]-[0132]), wherein the switched capacitor power conversion circuit ([0003]-[0004]) is configured to provide the output current (Figs. 1A & 2A; [0010]-[0017] & [0121]-[0123]: circuit is designed to deliver IOUT) to the output voltage node (Figs. 1A & 2A; [Abstract], [0083]-[0086], [Claim 4], [Claim 13], [Claim 14]: current is delivered to the node labeled VOUT, figures further illustrate the arrow for IOUT leaving the node labeled VOUT).
Claims 15-16 & 20 are rejected under 35 U.S.C. 103 as being unpatentable over Betser, in view of Walter, and further in view of Meyvaert et al. (US 2020/0144908 A1, Pub. Date May 7, 2020, hereinafter Meyvaert).
Regarding dependent claim 15, Betser, teaches:
The method of claim 1 ([Title], [Abstract], [0083], [0097], & [0125]-[0132]), and a measured current corresponding with IIN x N ([0121]-[0132], [0148], & [0166]-[0167]: discloses this calculation where N = 1 and Offset = 0 (ideal case) or accounting for parasitic error).
Betser, in combination with Walter, are silent in regard to:
wherein a value of Offset is determined by measuring a difference between a measured current corresponding with lOUT
However, Meyvaert, further teaches:
wherein a value of Offset is determined ([0011]-[0013]: teaches determining correction factors (efficiency/losses) to refine output current calculations) by measuring a difference between ([0011]-[0015]: teaches measuring the actual parameters to determine the loss relationship) a measured current corresponding with lOUT ([0011]-[0015]: teaches measuring the actual output current during a calibration phase)
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the calibration technique taught by Meyvaert (measuring IIN and IOUT to characterize the converter) to the estimation method of Betser/Walter, to determine the precise value of the “Offset” (parasitic current), therefore the combination of Bester (estimation method), Walter (multimode factor N), and Meyvaert (calibration method), render the claim obvious, where Meyvaert calculates efficiency (ratio), a POSITA understands that “Offset” in a linear equation (y=mx +b) is determined algebraically by measuring the input (x) and the output (y) and solving for the intercept (b), therefore measuring IOUT (dependent variable) and IIN x N (independent variable) and finding the difference yields the “Offset”, where Meyvaert measures IOUT (dependent variable) and IIN (independent variable scaled by an ideal ratio) to determine losses/correction factors, improving the accuracy desired by Betser ([0166]), ensuring estimated output current matching, where it has been held to be within the general skill of a worker in the art to employ and/or combine a known technique and/or elements according to known methods to improve similar devices (methods, products) in the same way is obvious, and yield predictable results (KSR).
Regarding dependent claim 16, Betser, teaches:
The method of claim 1 ([Title], [Abstract], [0083], [0097], & [0125]-[0132]), wherein a value of Offset ([0121]-[0132]: Offset corresponds to parasitic currents (Betser), quiescent losses (Walter) or calibration parameters/losses (Meyvaert))
Betser, in combination with Walter, are silent in regard to:
is programmed in a memory circuit for subsequent access.
However, Meyvaert, further teaches:
is programmed in a memory circuit ([0011]-[0015]: teaches storing determined calibration parameters in memory) for subsequent access ([0011]-[0015] & [0031]-[0034]: purpose of storing the value in a memory circuit is for use during the calculation step or “subsequence access”, or later use during the operation of the regulator).
It would have been obvious to one of ordinary skill in the art before the effective filing date to store the “Offset” determined by the calibration process of Meyvaert, or in combination with Betser/Walter, whose methodology also determine “Offset”, in a memory circuit, also taught by Meyvaert for “subsequent access” by the hardware processor, allowing the processor to quickly retrieve the stored offset value(s) during real-time operation to perform the estimation calculation without re-calibrating every cycle, where it has been held to be within the general skill of a worker in the art to employ and/or combine a known technique and/or elements according to known methods to improve similar devices (methods, products) in the same way is obvious, and yield predictable results (KSR).
Regarding dependent claim 20, Betser, teaches:
The method of claim 19 ([Title], [Abstract], [0011], [0083], [0097], & [0125]-[0132]), wherein a value of Offset ([0121]-[0132]: Offset corresponds to parasitic currents (Betser), quiescent losses (Walter) or calibration parameters/losses (Meyvaert))
Betser, in combination with Walter, are silent in regard to:
is programmed in a memory circuit for subsequent access.
However, Meyvaert, further teaches:
is programmed in a memory circuit ([0011]-[0015]: teaches storing determined calibration parameters in memory) for subsequent access ([0011]-[0015] & [0031]-[0034]: purpose of storing the value in a memory circuit is for use during the calculation step or “subsequence access”, or later use during the operation of the regulator).
It would have been obvious to one of ordinary skill in the art before the effective filing date to store the “Offset” determined by the calibration process of Meyvaert, or in combination with Betser/Walter, whose methodology also determine “Offset”, in a memory circuit, also taught by Meyvaert for “subsequent access” by the hardware processor, allowing the processor to quickly retrieve the stored offset value(s) during real-time operation to perform the estimation calculation without re-calibrating every cycle, where it has been held to be within the general skill of a worker in the art to employ and/or combine a known technique and/or elements according to known methods to improve similar devices (methods, products) in the same way is obvious, and yield predictable results (KSR).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. de Cremoux (US2023/0155472A1) discloses methods and systems for current sensing.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HUGO NAVARRO/ Examiner, Art Unit 2858 02/05/2026
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 2/6/2026