DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Applicant has not complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. 120 as follows:
The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application (the parent or original nonprovisional application or provisional application). The disclosure of the invention in the parent application and in the later-filed application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement. See Transco Products, Inc. v. Performance Contracting, Inc., 38 F.3d 551, 32 USPQ2d 1077 (Fed. Cir. 1994).
The disclosure of the prior-filed application, Application No.18/073,626, fails to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application.
Prior filled Application No.18/073,626 teaches a chip package structure comprising one chip placed in a designed die-bonding with a dam built around to define a region, but does not teach a chip package structure comprising two or more chips placed in a designed die-bonding with a dam built around to define a region, a dielectric layer formed on the second board surface to cover the lower electrode portion of each of the electrodes; a vertical conductive structure formed to be partially embedded into the dielectric layer, and provide an electrical path between the first die-bonding region and the second die-bonding region.
Therefore, Application No.18/073,626 is not supported by the prior filed Application No.18/073,626 Specification.
Accordingly, claims 1-10 are not entitled to the benefit of prior Application No.18/073,626.
Election/Restrictions
Claims 1-10 are pending.
Election of Species IA was made without traverse in the reply filed on 05/01/2026.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "9", and “D1, D2, D3, D4” have been used to designate the Dam. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "10", and “46” have been used to designate the Metal Shielding layer. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Reference characters "9",”6”, and “D1, D2, D3, D4” have been used to designate the Dam.
Reference character “6” has been used to designate a Dam, a conductive metal layer, a first conductive metal layer.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim1 and 5-7 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 14 and 15-17 of co-pending Application No18/073,626 (reference application) in view of Kim et al. (US20130049563A1-Kim63). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims under consideration are directed to a chip package structure with two chips and a dam made by printing and the conflicting claims are directed to a chip package structure with one chips and a dam. The package structure with two chips and a dam made by printing is anticipated by the chip package structure with one chip and a dam chip. The claims are compared in the table below:
Application 18/510,923 Liu et al. (US20240088049A1-Liu49)
Application 18/073,626 Liu et al (US20240071776A1-Liu76)
Claim 1
A chip package structure, comprising:
a first chip and a second chip;
a conductive substrate, including:
a substrate having
a first board surface and
a second board surface opposite to each other;
a plurality of vias penetrating through the first board surface and the second board surface,
wherein at least a part of the plurality of vias is disposed in
a first die-bonding region of the substrate
on which the first chip is to be arranged and
a second die-bonding region of the substrate on which the second chip is to be arranged; and
a plurality of electrodes
extending from the first board surface to the second board surface through the plurality of vias,
wherein each of the plurality of electrodes includes
an upper electrode portion and
a lower electrode portion,
the upper electrode part covers the first board surface, and
the lower electrode portion partially covers the second board surface;
a dielectric layer formed on the second board surface
to cover the lower electrode portion of each of the electrodes;
a vertical conductive structure formed
to be partially embedded into the dielectric layer and
provide an electrical path between the first die-bonding region and the second die-bonding region;
at least one dam formed to surround the first die-bonding region and
formed on the first board surface,
wherein the at least one dam has a height higher than a height of the first chip and the second chip; and
a metal shielding layer covers
the at least one dam and
a part of the first board surface that do not overlap with the plurality of electrodes.
Claim 14
A chip package structure, comprising:
a conductive substrate, including:
a substrate having
a first board surface and
a second board surface opposite to each other;
a plurality of vias penetrating through the first board surface and the second board surface,
wherein at least a part of the plurality of vias is disposed in
a first die-bonding region on which a chip is to be arranged; and
a plurality of electrodes
extending from the first board surface to the second board surface through the plurality of vias,
wherein each of the plurality of electrodes includes
an upper electrode portion and
a lower electrode portion,
the upper electrode part covers the first board surface, and
the lower electrode portion partially covers the second board surface;
at least one dam formed to surround the first die-bonding region and
formed on the first board surface,
wherein the at least one dam has a height higher than a height of the chip;
a metal shielding layer covers
the at least one dam and
a part of the first board surface that do not overlap with the plurality of electrodes.
The claim under examination is directed to a chip package structure with a conductive substrate, including:
a substrate having
a first board surface and
a second board surface opposite to each other;
a plurality of vias penetrating through the first board surface and the second board surface,
wherein at least a part of the plurality of vias is disposed in
a first die-bonding region of the substrate
on which the first chip is to be arranged;
a plurality of electrodes
extending from the first board surface to the second board surface through the plurality of vias,
wherein each of the plurality of electrodes includes
an upper electrode portion and
a lower electrode portion,
the upper electrode part covers the first board surface, and
the lower electrode portion partially covers the second board surface;
at least one dam formed to surround the first die-bonding region and
formed on the first board surface,
wherein the at least one dam has a height higher than a height of the first chip and the second chip; and
a metal shielding layer covers
the at least one dam and
a part of the first board surface that do not overlap with the plurality of electrodes.
The conflicting claims are directed to a chip package structure, comprising:
a conductive substrate, including:
a substrate having
a first board surface and
a second board surface opposite to each other;
a plurality of vias penetrating through the first board surface and the second board surface,
wherein at least a part of the plurality of vias is disposed in
a first die-bonding region on which a chip is to be arranged; and
a plurality of electrodes
extending from the first board surface to the second board surface through the plurality of vias,
wherein each of the plurality of electrodes includes
an upper electrode portion and
a lower electrode portion,
the upper electrode part covers the first board surface, and
the lower electrode portion partially covers the second board surface;
at least one dam formed to surround the first die-bonding region and
formed on the first board surface,
wherein the at least one dam has a height higher than a height of the chip;
a metal shielding layer covers
the at least one dam and
a part of the first board surface that do not overlap with the plurality of electrodes.
The chip package structure with a conductive substrate, including:
a substrate having
a first board surface and
a second board surface opposite to each other;
a plurality of vias penetrating through the first board surface and the second board surface,
wherein at least a part of the plurality of vias is disposed in
a first die-bonding region of the substrate
on which the first chip is to be arranged;
a plurality of electrodes
extending from the first board surface to the second board surface through the plurality of vias,
wherein each of the plurality of electrodes includes
an upper electrode portion and
a lower electrode portion,
the upper electrode part covers the first board surface, and
the lower electrode portion partially covers the second board surface;
at least one dam formed to surround the first die-bonding region and
formed on the first board surface,
wherein the at least one dam has a height higher than a height of the first chip and the second chip; and
a metal shielding layer covers
the at least one dam and
a part of the first board surface that do not overlap with the plurality of electrodes,
is anticipated by the chip package structure, comprising:
a conductive substrate, including:
a substrate having
a first board surface and
a second board surface opposite to each other;
a plurality of vias penetrating through the first board surface and the second board surface,
wherein at least a part of the plurality of vias is disposed in
a first die-bonding region on which a chip is to be arranged; and
a plurality of electrodes
extending from the first board surface to the second board surface through the plurality of vias,
wherein each of the plurality of electrodes includes
an upper electrode portion and
a lower electrode portion,
the upper electrode part covers the first board surface, and
the lower electrode portion partially covers the second board surface;
at least one dam formed to surround the first die-bonding region and
formed on the first board surface,
wherein the at least one dam has a height higher than a height of the chip;
a metal shielding layer covers
the at least one dam and
a part of the first board surface that do not overlap with the plurality of electrodes.
Liu76 fails to disclose a chip package structure comprising:
a first chip and a second chip;
a first die-bonding region of the substrate and
a second die-bonding region of the substrate on which the second chip is to be arranged; and
a dielectric layer formed on the second board surface
to cover the lower electrode portion of each of the electrodes;
a vertical conductive structure formed
to be partially embedded into the dielectric layer and
provide an electrical path between the first die-bonding region and the second die-bonding region;
wherein the at least one dam has a height higher than a height of the first chip and the second chip.
Kim63 teaches a chip package structure comprising:
a first chip and a second chip (Firs and second chips 230-Fig 12, [0260]);
a first die-bonding region of the substrate (330 on substrate 310b-Fig 12) and
a second die-bonding region of the substrate on which the second chip is to be arranged (330 on substrate 310b for second/Right chip-Fig 12); and
a dielectric layer formed on the second board surface (Dielectric layer 310a formed on substrate 310b-Fig 12, [0151])
to cover the lower electrode portion of each of the electrodes (310a covering lower electrode portion of each of the electrodes 294-Fig 9B, Fig 12);
a vertical conductive structure formed (321a/322a-Fig 12)
to be partially embedded into the dielectric layer (321a/322a embedded in dielectric layer 310a-Fig 12) and
provide an electrical path between the first die-bonding region and the second die-bonding region (In direct contact so having an electrical path from Left die to 321a to 305a to 321a to Right chip 230-Fig 12);
wherein the at least one dam has a height higher than a height of the first chip and the second chip (Dam 310c/d having a height higher than both chips 230-Fig 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the chip package of Liu76 as taught by Kim63 for the purpose of improving the light emission efficiency of the light emitting device package by increasing the reflecting area (Kim63: [161]).
MPEP 2112.01 states “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977)”.
Claim 5
The chip package structure according to claim 4,
wherein the at least one dam includes a plurality of printing layers, and
each of the printing layers is formed by performing
a printing step and
a curing step.
Claim 15
The chip package structure according to claim 14,
wherein the at least one dam includes a plurality of printing layers, and
each of the printing layers is formed by performing
a printing step and
a curing step.
Claim 6
The chip package structure according to claim 4,
wherein the at least one dam has a cross section formed by
a combination of one or more of a rectangle, a triangle, a half circle, a half ellipse, and a trapezoid.
Claim 16
The chip package structure according to claim 14,
wherein the at least one dam has a cross section formed by
a combination of one or more of a rectangle, a triangle, a half circle, a half ellipse, and a trapezoid.
Claim 7
The chip package structure according to claim 4,
wherein the height of the at least one dam is within a range from 50 to 1000 μm, and
a distance between the first die-bonding region and a vertical projection of the at least one dam projected onto the first board surface is at least greater than 100 μm.
Claim 17
The chip package structure according to claim 14,
wherein the height of the at least one dam is within a range from 50 to 1000 μm, and
a distance between the first die-bonding region and a vertical projection of the at least one dam projected onto the first board surface is at least greater than 100 μm
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the limitation "the electrodes" in line L17, renders the claim indefinite because the antecedent basis is unclear as to whether "the electrodes" in line L17 refers to new electrodes or the “plurality of electrodes” previously cited in Claim 1 Line L11. In the purpose of compact prosecution, “the electrodes” has been interpretated as the plurality of electrodes.
Regarding claim 4, the limitation "the first vertical conductive structure" in lines L1-2, renders the claim indefinite because the antecedent basis is unclear as to whether "the first vertical conductive structure" in lines L1-2, refers to a new first vertical conductive structure or the "vertical conductive structure" previously cited in Claim 1 Line L18. In the purpose of compact prosecution, “the first vertical conductive structure” has been interpretated as the vertical conductive structure.
Regarding claim 8, the limitation "the electrodes" in lines L2 and L4, renders the claim indefinite because the antecedent basis is unclear as to whether "the electrodes" in lines L2 and L4, refers to new electrodes or the “plurality of electrodes” previously cited in Claim 1 Line L11. In the purpose of compact prosecution, “the electrodes” has been interpretated as the plurality of electrodes.
The balance of claims are rejected for being dependent upon an already rejected claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US9985191B2-Chiu91) in view of Kim et al. (US20130049563A1-Kim63).
Regarding claim 1, Chiu91 discloses a chip package structure (Title), comprising:
a first chip (First Chip 21);
a conductive substrate (Conductive substrate 1 being conductive because of the conductive vias 15-Examiner's annotated Fig 15), including:
a substrate having a first board surface (First surface board 111-See Examiner's annotated Fig 15) and
a second board surface opposite to each other (Second board surface 112 opposite to First board surface 111-See Examiner's annotated Fig 15);
a plurality of vias penetrating through the first board surface and the second board surface (Plurality of vias 15 penetrating first board surface 111 and second board surface 112-See Examiner's annotated Fig 15),
wherein at least a part of the plurality of vias is disposed in a first die-bonding region of the substrate on which the first chip is to be arranged (at least a part of the plurality of vias 15 being disposed in a first die-bonding region 131 of the substrate on which first chip 21 being arranged-See examiner's annotated Fig 15); and
a plurality of electrodes extending from the first board surface to the second board surface through the plurality of vias (electrodes are filling vias 15 extending from the first board surface 111 to the second board surface 112-See Examiner's annotated Fig 15),
wherein each of the plurality of electrodes includes
an upper electrode portion (133, 131, 132-See Examiner’s annotated Fig 15) and
a lower electrode portion (142, 141, 142-See Examiner's annotated Fig 15),
the upper electrode part portion covers the first board surface (the upper electrode parts 133, 131, 132 cover the first board surface 111-See Examiner's annotated Fig 15), and
the lower electrode portion partially covers the second board surface (the lower electrode parts 142, 141, 142 cover the first board surface 112-See Examiner's annotated Fig 15);
at least one dam formed to surround the first die-bonding region and formed on the first board surface (Dam 52 surrounding first-die-forming region 13 and formed on first surface board 111-See Examiner's annotated Fig 15),
wherein the at least one dam has a height higher than a height of the first chip (Dam 52 height is higher than chip 21 height-See Examiner's annotated Fig 15); and
a metal shielding layer covers the at least one dam and a part of the first board surface that do not overlap with the plurality of electrodes (Metal shielding layer 53+17, light-shielding portion 17 being a metallic layer disposed on the top surface 111 that does not overlap with electrodes 131, 132, 133 - C5L40-41 and Fig 12; a reflecting layer 53 covers the dam 52-See Examiner's annotated Fig 15; the layer 53 is aluminum so a metal shielding layer-C6L30).
Chiu91 does not disclose a chip package structure
a second chip;
wherein at least a part of the plurality of vias is disposed in a second die-bonding region of the substrate on which the second chip is to be arranged;
a dielectric layer formed on the second board surface
to cover the lower electrode portion of each of the electrodes;
a vertical conductive structure formed
to be partially embedded into the dielectric layer and
provide an electrical path between the first die-bonding region and the second die-bonding region;
wherein the at least one dam has a height higher than a height of the second chip.
Kim63 teaches a chip package structure comprising:
a second chip (First/Left and second/Right chips 230-Examiner's annotated Fig 12, [0260]);
wherein at least a part of the plurality of vias is disposed in a second die-bonding region of the substrate on which the second chip is to be arranged (Vias 321a/322a disposed in Second/Right die-bonding region 330 on substrate 310b for second/Right chip-Examiner's annotated Fig 12); and
a dielectric layer formed on the second board surface (Dielectric layer 310a formed on substrate 310b-Examiner's annotated Fig 12, [0151])
to cover the lower electrode portion of each of the electrodes (Dielectric layer 310a covering lower electrode portion of each of the electrodes 294-Fig 9B, Examiner's annotated Fig 12);
a vertical conductive structure formed (vertical conductive structure 321a/322a-Examiner's annotated Fig 12)
to be partially embedded into the dielectric layer (vertical conductive structure 321a/322a embedded in dielectric layer 310a-Fig 12) and
provide an electrical path between the first die-bonding region and the second die-bonding region (In direct contact so having an electrical path from Left die to 321a to 305a to 321a to Right chip 230-Examiner's annotated Fig 12);
wherein the at least one dam has a height higher than a height of the first chip and the second chip (Dam 310c/d having a height higher than both chips 230-Fig 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the chip package of Chiu91 as taught by Kim63 for the purpose of improving the light emission efficiency of the light emitting device package by increasing the reflecting area (Kim63: [161]).
Regarding claim 2, Chiu91 and Kim63 combination teaches all the elements of claim 1, as noted above.
Kim63 further teaches chip package structure
wherein a first via is formed in the dielectric layer to correspond to a first electrode of the plurality of electrodes in the first die-bonding region (First/Left via 321a formed in dielectric layer 310a corresponding to first electrode 294 in first/left die-bonding region 330-Examiner's annotated Fig 12), and
a second via is provided in the dielectric layer to correspond to a second electrode of the plurality of electrodes in the second die-bonding region (Second/Right via 321a formed in dielectric layer 310a corresponding to Second/Right electrode 294 in Second/Right die-bonding region 330-Examiner's annotated Fig 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the chip package of Chiu91 as taught by Kim63 for the purpose of improving the light emission efficiency of the light emitting device package by increasing the reflecting area (Kim63: [161]).
Regarding claim 3, Chiu91 and Kim63 combination teaches all the elements of claim 2, as noted above.
Kim63 further teaches chip package structure
wherein the first via and the second via penetrate through a lower surface of the dielectric layer (First/Left via 321a and the second/Right via 321a penetrating through a lower surface of the dielectric layer 310a-Examiner's annotated Fig 12),
there by exposing a part of the lower electrode portion of each of the first electrode and the second electrode (First/Left vias and Second/Right vias 321a/322a exposing lower electrode portion of electrodes 294-Examiner's annotated Fig 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the chip package of Chiu91 as taught by Kim63 for the purpose of improving the light emission efficiency of the light emitting device package by increasing the reflecting area (Kim63: [161]).
Regarding claim 4, Chiu91 and Kim63 combination teaches all the elements of claim 3, as noted above.
Kim63 further teaches chip package structure
wherein the first vertical conductive structure includes:
a first metal conductor (Vertical conductive structure 321a/322a with First/Left metal conductor in First/Left vias 321a-Examiner's annotated Fig 12, Fig 15, [0184]) and
a second metal conductor formed in the first via and the second via, respectively (Vertical conductive structure 321a/322a with Second/Right metal conductor in Second/Right vias 321a-Examiner's annotated Fig 12, Fig 15, [0184]); and
a metal sheet formed on the lower surface of the dielectric layer to electrically connect the first metal conductor with the second metal conductor, so as to establish the electrical path between the first die-bonding region and the second die-bonding region (Metal sheet 305a formed on lower surface of dielectric layer 310a connecting First/Left metal conductor in First/Left vias 321a with Second/Right metal conductor in Second/Right vias 321a to create Electric path between First/Left die-bonding region 330 and Second/Right die-bonding region 330-Examiner's annotated Fig 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the chip package of Chiu91 as taught by Kim63 for the purpose of improving the light emission efficiency of the light emitting device package by increasing the reflecting area (Kim63: [161]).
Regarding claim 6, Chiu91 and Kim63 combination teaches all the elements of claim 4, as noted above.
Chiu91 further discloses a chip package structure
wherein the at least one dam has a cross section formed by a combination of one or more of
a rectangle,
a triangle,
a half circle,
a half ellipse, and
a trapezoid (Dam 52 has a trapezoid shape-See Examiner's annotated Fig 15, C6 L8).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US9985191B2-Chiu91) in view of Kim et al. (US20130049563A1-Kim63), and further in view of Pruett et al. (US 20150352786 A1-Pruett86).
Regarding claim 5, Chiu91 and Kim63 combination teaches all the elements of claim 4, as noted above.
Chiu91 and Kim63 combination does not teach a chip package structure
wherein the at least one dam includes a plurality of printing layers, and
each of the printing layers is formed by performing
a printing step and
a curing step.
Pruett86 teaches a chip package structure
wherein the at least one dam includes a plurality of printing layers (Dam 104/106/110 with Dam including several printing layers-Fig 2, Fig 17, [0004] L1-15), and
each of the printing layers is formed by performing
a printing step ([0004] L1-15) and
a curing step ([0004] L1-15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the chip package of Chiu91 in view of Kim63, as taught by Pruett86 for the purpose of improving the light emission efficiency of the light emitting device package by keeping the dam free of pinholes (Pruett86: [0038]).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US9985191B2-Chiu91) in view of Kim et al. (US20130049563A1-Kim63), and further in view of Lin et al. (US20200135991A1-Lin91).
Regarding claim 7, Chiu91 and Kim63 combination teaches all the elements of claim 4, as noted above.
Kim63 further teaches a chip package structure
wherein the height of the at least one dam is within a range from 50 to 1000µm (third layer 213 in range of 40 to 60µm, layer 211, 212, 213, 214, 215 may have the same number of layers so same thickness so dam 211/212 being at least 80µm-Fig 7, [0118] L1-5, [0121] L11-13).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the chip package of Chiu91 as taught by Kim63 for the purpose of improving the light emission efficiency of the light emitting device package by increasing the reflecting area (Kim63: [161]).
Chiu91 and Kim63 combination does not teach a chip package structure wherein
a distance between the first die-bonding region and a vertical projection of the at least one dam projected onto the first board surface is at least greater than 100 µm.
Lin91 teaches a chip package structure wherein
a distance between the first die-bonding region and a vertical projection of the at least one dam projected onto the first board surface is at least greater than 100 µm (the thickness of the light-transmissive encapsulant 13 and the light-transmissive wall or dam 14 is 0.55mm or 550 μm, so larger than 100μm -[066] L10, Fig 8K).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the chip package structure of Chiu91 as taught by Lin991 for the purpose of increasing the viewing angle (Lin91: [0006]).
Claim(s) 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US9985191B2-Chiu91) in view of Kim et al. (US20130049563A1-Kim63, and further in view of Qin et al. (US20180062048A1-Qin48).
Regarding claim 8, Chiu91 and Kim63 combination teaches all the elements of claim 4, as noted above.
Kim63 further teaches a chip package structure
wherein the first chip disposed in the first die-bonding region is electrically connected to the electrodes in the first die-bonding region (First/Left Chip 230 on First/Left die-bonding region 330, in direct contact so electrically connected to electrode 321a-Examiner's annotated Fig 12), and
the second chip disposed in the second die-bonding region is electrically connected to the electrodes in the second die-bonding region (Second/Right Chip 230 on Second/Right die-bonding region 330, electronically connected to electrode 321a-Examiner's annotated Fig 12); and
a package cover disposed and fixed on the metal shielding layer (Package cover 5 is fixed on metal shielding layer 17+53-See Examiner's annotated Fig 15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the chip package of Chiu91 as taught by Kim63 for the purpose of improving the light emission efficiency of the light emitting device package by increasing the reflecting area (Kim63: [161]).
Chiu91 and Kim63 combination does not teach a chip package structure
wherein the package cover, the at least one dam and the conductive substrate jointly define
a first enclosed space surrounding the first chip and
a second enclosed space surrounding the second chip.
Qin48 teaches a chip package structure
wherein the package cover, the at least one dam and the conductive substrate jointly define
a first enclosed space surrounding the first chip (dam 77, Substrate 71, package cover 93 defining a first/left enclosed space surrounding first/left chip 91-Fig 8, Fig 9) and
a second enclosed space surrounding the second chip (dam 77, Substrate 71, package cover 93 defining a second/right enclosed space surrounding second/right chip 91-Fig 8, Fig 9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the chip package of Chiu91 in view of Kim63, as taught by Qin48 for the purpose of improving the extraction efficiency of light in a light-transmissive encapsulation (Qin48: [0034]).
Regarding claim 9, Chiu91 and Kim63 combination teaches all the elements of claim 8, as noted above.
Kim63 further teaches a chip package structure
wherein the first chip and the second chip are light-emitting diode chips (Both chips 230 being LED-[0155]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the chip package of Chiu91 as taught by Kim63 for the purpose of improving the light emission efficiency of the light emitting device package by increasing the reflecting area (Kim63: [161]).
Regarding claim 10, Chiu91 and Kim63 combination teaches all the elements of claim 8, as noted above.
Chiu91 further discloses a chip package structure
wherein an inner side surface of the at least one dam facing the first chip or the second chip is inclined at a predetermined angle relative to the conductive substrate (Predetermined angle of inner side of Dam 52 covered with metal shielding 53 relative to the substrate 1-Examiner's annotated Fig 15),
such that the metal shielding layer on the inner side surface is also inclined relative to the conductive substrate at the predetermined angle (Predetermined angle of inner side of Dam 52 covered with metal shielding 53 relative to the substrate 1-Examiner's annotated Fig 15), and
the package cover is a transparent cover (Package cover 5 is translucent so transparent-C5 L66-67).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lin et al. (US20200135991A1) teaches discloses a chip package structure (Title), comprising: a first chip (First/left Chip 12-Fig 4); a conductive substrate (Conductive substrate 11, the substrate can be a metal so conductive-[0052] Lines L4-5, Fig 4) including: a substrate having a first board surface (Top surface of substrate 11-Fig 4) and a second board surface opposite to each other (Bottom surface opposite to top surface-4); and a trapezoid dam (143-Fig 4).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 06/03/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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