DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-5 and 8-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11869951. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Regarding claim 1, the claims of U.S. Patent No. 11869951 disclose an integrated chip (see claim 1), comprising:
an erase gate and a word line elongated in a first dimension (see claim 1); and
a control gate elongated in the first dimension and between and bordering the erase gate and the word line (see claim 1),
wherein the control gate has a first protrusion and a second protrusion that are recessed respectively into the erase gate and the word line and that form a first pad (see claim 1),
wherein the first protrusion is between and protrudes from a first sidewall of the control gate and a second sidewall of the control gate, both of which face the erase gate (see claim 1), and
wherein the second protrusion is between and protrudes from a third sidewall of the control gate and a fourth sidewall of the control gate, both of which face the word line (see claim 1).
Regarding claim 2, the claims of U.S. Patent No. 11869951 disclose the integrated chip according to claim 1, wherein a separation between the first and third sidewalls is the same as a separation between the second and fourth sidewalls (see claim 23).
Regarding claim 3, the claims of U.S. Patent No. 11869951 disclose the integrated chip according to claim 1, wherein the first and second protrusions are symmetrical about an axis extending laterally in a second dimension orthogonal to the first dimension (see claim 11).
Regarding claim 4, the claims of U.S. Patent No. 11869951 disclose the integrated chip according to claim 1, wherein the first and second sidewalls extend along a first axis, which extends laterally in the first dimension, and wherein the third and fourth sidewalls extend along a second axis parallel to the first axis (see claim 1).
Regarding claim 5, the claims of U.S. Patent No. 11869951 disclose the integrated chip according to claim 1, wherein the control gate comprises a second pad spaced from the first pad in the first dimension, and wherein the first and third sidewalls have a constant separation from the first pad to the second pad (see claim 1).
Regarding claim 8, the claims of U.S. Patent No. 11869951 disclose an integrated chip, comprising:
an erase gate and a word line elongated in a first dimension (see claim 1); and
a first control gate elongated in the first dimension and between and bordering the erase gate and the word line (see claim 1),
wherein the first control gate has a first pad that is recessed into the erase gate at a first sidewall indent of the erase gate and that is recessed into the word line at a first sidewall indent of the word line (see claim 1), and
wherein the first pad, the first sidewall indent of the erase gate, and the first sidewall indent of the word line are symmetrical about a first axis, which extends laterally in a second dimension orthogonal to the first dimension (see claim 11).
Regarding claim 9, the claims of U.S. Patent No. 11869951 disclose the integrated chip according to claim 8, wherein the erase gate has a pair of sidewalls facing each other in the first sidewall indent of the erase gate, and wherein the pair of sidewalls of the erase gate have individual lengths that extend laterally in the second dimension and that are the same (see claim 23).
Regarding claim 10, the claims of U.S. Patent No. 11869951 disclose the integrated chip according to claim 9, wherein the word line has a pair of sidewalls facing each other in the first sidewall indent of the word line, and wherein the pair of sidewalls of the word line have individual lengths that extend laterally in the second dimension and that are the same (see claim 23).
Regarding claim 11, the claims of U.S. Patent No. 11869951 disclose the integrated chip according to claim 8, wherein the first control gate has a second pad spaced from the first pad in the first dimension and recessed into the word line at a second sidewall indent of the word line, wherein the word line has a substantially uniform width from the first sidewall indent of the word line to the second sidewall indent of the word line, and wherein the substantially uniform width extends laterally in the second dimension (see claims 1 and 10).
Regarding claim 12, the claims of U.S. Patent No. 11869951 disclose the integrated chip according to claim 8, further comprising: a second control gate elongated in the first dimension on an opposite side of the erase gate as the first control gate, wherein the second control gate has a first pad that is recessed into the erase gate at a second sidewall indent of the erase gate, wherein the erase gate has a substantially uniform width from the first sidewall indent of the erase gate to the second sidewall indent of the erase gate, and wherein the substantially uniform width extends laterally in the second dimension (see claim 14).
Regarding claim 13, the claims of U.S. Patent No. 11869951 disclose the integrated chip according to claim 12, wherein the first pad of the second control gate and the second sidewall indent of the erase gate are symmetrical about a second axis parallel to the first axis (see claim 11).
Allowable Subject Matter
Claims 6 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record does not teach or suggest, singularly or in combination, at least a device comprising “an erase gate and a word line elongated in a first dimension; and a control gate elongated in the first dimension and between and bordering the erase gate and the word line, wherein the control gate has a first protrusion and a second protrusion that are recessed respectively into the erase gate and the word line and that form a first pad, wherein the first protrusion is between and protrudes from a first sidewall of the control gate and a second sidewall of the control gate, both of which face the erase gate, and wherein the second protrusion is between and protrudes from a third sidewall of the control gate and a fourth sidewall of the control gate, both of which face the word line” as required by claim 1 and further “wherein the first protrusion has a semicircular top geometry with a curved sidewall arcing continuously from the first sidewall to the second sidewall” as required by claim 6 or “wherein the first protrusion has a first rectangular top geometry and is recessed into a sidewall of the erase gate at a sidewall indent, which has a second rectangular top geometry” as required by claim 7, both of which depend on claim 1. This represents the main differences between the devices of claims 6 and 7 and the prior art of record.
Claims 14-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record does not teach or suggest, singularly or in combination, at least an integrated chip, comprising: a first word line and a second word line elongated in parallel in a first dimension; a first control gate and a second control gate elongated in parallel in the first dimension and between and respectively bordering the first and second word lines, wherein the first and second control gates respectively comprise a first pad and a second pad; and an erase gate between and bordering the first and second control gates; wherein the first word line has a first width value that is in a first cross-sectional plane overlapping with the first pad and that is less than a first width of the second word line in the first cross-sectional plane, wherein the first control gate has a first width value that is in the first cross-sectional plane and that is more than a first width value of the second control gate in the first cross-sectional plane, wherein the first word line has a second width value that is in a second cross-sectional plane overlapping with the second pad and that is more than a second width of the second word line in the second cross-sectional plane, and wherein the first control gate has a second width value that is in the second cross-sectional plane and that is less than a second width value of the second control gate in the second cross-sectional plane”. This represents the main difference between the device of claim 14 and the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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