Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 12-31 in the reply filed on 14 April 2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 12, 15, 20-23, 25-28, 30 and 31 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipate by Cho et al. (US Pat. Pub. 2021/0005533).
Regarding claim 12, Cho teaches a method of forming an integrated chip, comprising:
performing a first etching process on a substrate to form one or more sidewalls of the substrate that form a first through-substrate-via (TSV) opening extending through the substrate [fig. 2b, recess R1 formed in substrate 101];
forming a dielectric liner along the one or more sidewalls of the substrate [fig. 2b, dielectric liner 104];
forming an etch blocking layer onto one or more sidewalls of the dielectric liner and within the first TSV opening [fig. 2c, 105p];
performing a second etching process on the dielectric liner, with the etch blocking layer on the one or more sidewalls of the dielectric liner, to form a second TSV opening extending through the dielectric liner [fig. 2d, paragraph [0045]]; and
forming a through-substrate-via within the first TSV opening and the second TSV opening, wherein the through-substrate-via has a larger width along a top surface of the through-substrate-via than directly between closest parts of sidewalls of the etch blocking layer [fig. 1a, through substrate via 107/TE, 107 portion of the via has a larger width along the top surface than between the closest parts of the sidewalls of the etch blocking layer].
Regarding claim 15, Cho discloses the method of claim 12, wherein the etch blocking layer completely covers a part, but not all, of the one or more sidewalls of the dielectric liner during the second etching process [figs. 2c and 2d, 105 covers a part of the sidewall of 104 during the second etching process].
Regarding claim 20, Cho teaches the method of claim 12, wherein forming the through substrate via within the first TSV opening and the second TSV opening comprises:
Depositing a conductive material within the first TSV opening and the second TSV opening; and
Performing a planarization process to remove a part of the conductive material [paragraph [0048] teaches forming a conductive material in the openings and planarizing said material].
Regarding claim 21, Cho discloses a method of forming an integrated chip, comprising:
forming a plurality of interconnects within a dielectric structure along a first side of a substrate [fig. 2a, interconnects 400, 102c, 102p in dielectric 102 on first side of substrate 101];
performing a first etching process on a second side of the substrate to form a first through-substrate-via (TSV) opening extending through the substrate [fig. 2b, recess R1 in substrate 101];
forming a dielectric liner along one or more sidewalls of the substrate and on one or more horizontally extending surfaces of the dielectric structure that form the first TSV opening [fig. 2b, 104];
forming an etch blocking layer onto one or more sidewalls of the dielectric liner [fig. 2c, 105p];
performing a second etching process, with the etch blocking layer on the one or more sidewalls of the dielectric liner, to form a second TSV opening that extends through the dielectric liner and a part of the dielectric structure to expose one of the plurality of interconnects [fig. 2d, paragraph [0045]]; and
forming a conductive material within the first TSV opening and the second TSV opening [fig. 1a, 107/TE within the first and second TSV openings].
Regarding claim 22, Cho teaches the method of claim 21, wherein the first TSV opening has a larger maximum width than the second TSV opening [fig. 2d, the first opening 301 has a larger maximum width than the second opening 302].
Regarding claim 23, Cho teaches the method of claim 21, wherein the conductive material has a first sidewall within the first TSV opening, a second sidewall with in the second TSV opening and a horizontally extending surface between the first sidewall and the second sidewall [fig. 1a, TE has first sidewall at 301, a second sidewall at 302 and a horizontal surface at the bottom of 301 where the liner 104 extends across the bottom of the first opening].
Regarding claim 25, Cho discloses the method of claim 21, wherein the dielectric liner comprises an oxide [paragraph [0026]], and the blocking layer comprises a nitride [paragraph [0043]].
Regarding claim 26, Cho teaches the method of claim 21, wherein the second TSV opening is laterally set back from opposing outer edges of the first TSV opening by non-zero distances [fig. 2d, the second opening 302 is narrower than the first opening 301, therefore the second opening is laterally set back from opposing outer edges of the first opening].
Regarding claim 27, Cho discloses a method of forming an integrated chip, comprising:
forming a plurality of interconnects within an inter-level dielectric (ILD) structure along a first side of a substrate [fig. 2a, ILD 102, interconnects 102p, 102c and 400];
performing a plurality of separate etching processes to form a TSV opening that extends through the substrate and into the ILD structure to expose a first interconnect of the plurality of interconnects [fig. 2d, first and second etching processes form 301 and 302, exposing interconnects through the substrate], wherein the TSV opening has a first width measured along a bottom of the TSV opening, a second width measured over the first width, and a third width measured over the second width, the second width being larger than the first width and the third width [fig. 2d, first width at the bottom of 302, second width at 301, third width at 0p, second width wider than first and third]; and
forming a conductive material within the TSV opening [fig. 1a, 107/TE filling the TSV opening].
Regarding claim 28, Cho teaches the method of claim 27, wherein the plurality of separate etching processes comprises a first etching process that etches through the substrate and a second etching process that etches through the ILD structure to expose the first interconnect [figs. 2b-2c demonstrate a first etch that etches through the substrate and a second etch that expose the interconnect].
Regarding claim 30, Cho discloses the method of claim 28, further comprising: forming a dielectric liner onto the substrate and the ILD structure between the first etching process and the second etching process [fig. 2b, liner 104, formed after the etch process]; and
forming an etch blocking layer onto one or more sidewalls of the dielectric liner between the first etching process and the second etching process [fig. 2c, blocking layer 105p before the second etching process].
Regarding claim 31, Cho teaches the method of claim 30, further comprising:
Forming the conductive material within the TSV opening and onto sidewalls of both the dielectric liner and the etch blocking layer [fig. 1a, TE/107 is formed onto sidewalls of 104 and 105].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho as applied to claims 12, 15, 20-23, 25-28, 30 and 31 above, and further in view of Weng et al. (US Pat. Pub. 2020/0006128).
Regarding claim 16, Cho fails to teach the etch blocking layer completely covers the one or more sidewalls of the dielectric liner during the second etching process. However, Weng shows a TSV interconnect structure formed by multiple etching steps including a step where a blocking layer completely covers sidewalls of a dielectric liner in a recess of a substrate during an etching process [fig. 6, substrate 120, liner 28, blocking layer 30, paragraph [0042] teaches 30 is used as a mask during etching].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Weng into the method of Cho by using an etch blocking layer that completely covers the sidewalls of the dielectric liner during the second etching process. The ordinary artisan would have been motivated to modify Cho in the manner set forth above for at least the purpose of utilizing know effective methods of protecting existing layers during etching steps to etch underlying structures [Weng, paragraphs [0041 and 0042]].
Regarding claim 17, Cho in view of Weng teaches the method of claim 16, further comprising:
Removing the etch blocking layer after performing the second etching process [Weng, fig. 7, 30 has been removed after etching].
Regarding claim 18, Cho in view of Weng discloses the method of claim 12, wherein the etch blocking layer comprises photosensitive material [Weng, paragraph [0041]].
Claim(s) 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho as applied to claims 12, 15, 20-23, 25-28, 30 and 31 above, and further in view of Chen et al. (US Pat. Pub. 2016/0155685).
Regarding claim 29, Cho teaches the second etching process is an anisotropic etching process [paragraph [0045]], but fails to teach the first etching process is a Bosch etching process.
However, Chen teaches forming through substrate openings using Bosch etching processes [paragraphs [0015-0017]].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Chen into the method of Cho by using a Bosch etching process as the first etching process. The ordinary artisan would have been motivated to modify Cho in the manner set forth above for at least the purpose of creating through substrate conductors with better noise shielding and preventing interference [Chen, paragraph [0026]].
Allowable Subject Matter
Claims 13, 14, 19 and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M PARKER whose telephone number is (571)272-8794. The examiner can normally be reached M-F 7:30am - 3:30pm.
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/JOHN M PARKER/Primary Examiner, Art Unit 2899
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