Prosecution Insights
Last updated: August 18, 2026
Application No. 18/511,029

SEMICONDUCTOR DEVICE WITH RESISTANCE MODIFICATION DOPED REGION

Non-Final OA §102§103§112
Filed
Nov 16, 2023
Priority
Aug 25, 2023 — divisional of 18/238,022
Examiner
STEPHENSON, KENNETH STEPHEN
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
NANYA TECHNOLOGY Corporation
OA Round
1 (Non-Final)
71%
Grant Probability
Favorable
1-2
OA Rounds
10m
Est. Remaining
80%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allowance Rate
5 granted / 7 resolved
+3.4% vs TC avg
Moderate +8% lift
Without
With
+8.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
26 currently pending
Career history
49
Total Applications
across all art units

Statute-Specific Performance

§101
3.9%
-36.1% vs TC avg
§103
40.6%
+0.6% vs TC avg
§102
26.1%
-13.9% vs TC avg
§112
26.7%
-13.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 7 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 13 – 16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 4 May 2026. Applicant’s election without traverse of Invention I—Claims 1 – 12—and Species V—Fig. 6—in the aforementioned reply is acknowledged. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: MOSFET-TYPE ANTI-FUSE DEVICE WITH NITRIDE CHANNEL INCLUSIONS. The disclosure is objected to because of the following informalities: Par. 51 discloses “the resistance modification doped region 224 may make the fuse medium 231 to be an ohmic type fuse when the fuse medium 231 is blown out”. However, this appears to be written in error, where the accurate text appears to be “the resistance modification doped region 224 may make the fuse Par. 59 discloses “the impurity 271 and/or 272 may modify the resistance of the fuse and make the fuse medium 231 to be an ohmic type fuse”. However, this appears to be written in error, where the accurate text appears to be “the impurity 271 and/or 272 may modify the resistance of the fuse and make the fuse Throughout the specification, “fuse” is mentioned 120 times. However, at no point does the instant specification or the specification of the parent application 18/056,181 clarify that “fuse” may also or instead mean “anti-fuse”. Further, Applicant’s disclosure clearly describes an anti-fuse and not a fuse as the invention. As these terms have substantially different meanings, for the sake of clarity of the record, every instance of “fuse” in the instant specification should be amended read “anti-fuse”. Appropriate correction is required. Claim Objections Claim 10 is objected to because of the following informalities: Lin. 1 – 2 recite “a concentration of the nitrogen derivative impurities is gradient” where “gradient” is used as an adjective but is a noun, which is grammatically improper and unclear. For clarity of the record, the claim language should be amended. The suggested amended language and the interpretation of the original language for the purposes of examination is “a concentration of the nitrogen derivative impurities comprises a is gradient” . Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1, 4, 6 – 9, & 11—as well as their respective dependent claims—are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Regarding Claims 1, 4, 6 – 9, & 11, Each of these claims recites the term “fuse” at least once. However, this language is ambiguous, as Applicant is clearly claiming and disclosing an “anti-fuse” device, which is fundamentally different than a “fuse” and, therefore, renders these claims indefinite. The language of the claims must clearly and precisely define the metes and bounds of the claimed invention, since patented claims place the public on notice of the scope of the patentee's right to exclude. It is important that a person of ordinary skill in the art be able to interpret the metes and bounds of the claims so as to understand how to avoid infringement of the patent that ultimately issues from this application. For the purposes of examination, every instance of “fuse” in the claims will be interpreted as “anti-fuse”. Further regarding Claim 8, Lin. 1 – 2 recite “The semiconductor device of claim 7, wherein a resistance of the fuse medium is positively proportional to a temperature”. Admittedly, the instant specification does disclose “the impurity 271 and/or 272 may modify the resistance of the fuse [i.e. the semiconductor device] and make the fuse medium 231 to be an ohmic type fuse”, Par. 59, and “the resistance of an ohmic type fuse is positively proportional to a temperature”, Par. 9, which appears to be consistent with this claim. However, the meaning of this claim remains unclear, as it fails to meet the metes and bounds of the disclosed invention in that the instant specification also appears to be inconsistent with itself, as Par. 9 also states “the resistance modification doped region may make a fuse [as a whole rather than the fuse medium, specifically] to be an ohmic type fuse when a fuse medium is blown out under an operation current” where “the resistance modification doped region” and “the impurities 271/272” appear to be presented as alternative parts for different species (e.g. Fig. 2 vs. Fig. 6) of the claimed semiconductor device—i.e. the fuse—these parts providing the same function of making the fuse as a whole—i.e. the semiconductor device—an ohmic type fuse as opposed to making the fuse medium, specifically, an ohmic type fuse. Further, the impurities 271/272 are not disclosed to be within or a part of the fuse medium 231, (See Par. 57 – 61 and Fig. 6). As such, it is unclear how these impurities 271/272 could alter the properties of the fuse medium 231, specifically. In contrast, the ability of the impurities 271/272 to alter the properties of the fuse as a whole appears clear. Therefore, in light of these circumstances, it appears there is a minor error in Par. 59 of the instant specification, where the alteration “the impurity 271 and/or 272 may modify the resistance of the fuse and make the fuse As such, for the purposes of examination, this claim will be interpreted as “The semiconductor device of claim 7, wherein a resistance of the semiconductor device Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 4, & 7 – 11 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by CHIDAMBARRAO (US 20040051162 A1). Regarding Claim 1, CHIDAMBARRAO discloses: A semiconductor device (Fig. 4: 10), comprising: a substrate (14); a well region (localized region of 14 under 30) within the substrate (14) with a first conductive type (Par. 20, p-type); a anti-fuse medium (16) disposed over the substrate (14); a gate electrode (12) disposed over the anti-fuse medium (16); a anti-fuse doped region (28) under the gate electrode (12) with a second conductive type (Par. 20, n-type) different from first conductive type (p-type); a source/drain (S/D) region (26) adjacent to the anti-fuse doped region (28) with the second conductive type (Par. 20, n-type); and nitrogen derivative impurities (Par. 20, comprising implanted nitrogen ions) within the substrate (14) and under the gate electrode (12). (Under a broad but reasonable interpretation, as nitrogen ions are derived from molecular nitrogen, the implanted nitrogen ions may be construed to be a type of nitrogen derivative impurity. Further, Par. 20 discloses said nitrogen ions are implanted into 28, which is within 14 and under 12.) Regarding Claim 4, CHIDAMBARRAO discloses: The semiconductor device of claim 1, wherein the nitrogen derivative impurities are located within the anti-fuse doped region (28). (Par. 20) Regarding Claim 7, CHIDAMBARRAO discloses: The semiconductor device of claim 1, wherein the anti-fuse medium (16) is configured to be blown under a current ranging from about 0.4mA to about 1.2mA. (Par. 15) Regarding Claim 8, CHIDAMBARRAO discloses: The semiconductor device of claim 7, wherein a resistance of the semiconductor device is positively proportional to a temperature. (A resistance of the semiconductor device includes the resistance of its tungsten plugs 24, Par. 20, and the resistance of tungsten increases with increasing temperature. Therefore, the resistance of the tungsten plugs is positively proportional to a temperature within a sufficiently small temperature range such that a linear approximation of the resistance of the tungsten as a function of temperature is valid.) Regarding Claim 9, CHIDAMBARRAO discloses: The semiconductor device of claim 1, wherein the anti-fuse doped region (28) is in contact with the S/D region (26). (As seen in Fig. 4) Regarding Claim 10, CHIDAMBARRAO discloses: The semiconductor device of claim 1, wherein a concentration of the nitrogen derivative impurities comprises a gradient. (Par. 20 describes the nitrogen ions as being implanted in 28 via an ion implantation process. Therefore, the concentration of the nitrogen ions in 28 inherently comprises a gradient due to the nature of ion implantation processes.) Regarding Claim 11, CHIDAMBARRAO discloses: The semiconductor device of claim 1, further comprises: nitrogen atoms located within the anti-fuse doped region (28). (As described for Claim 1, nitrogen ions are located within 28. As nitrogen ions comprise nitrogen atoms, nitrogen atoms are also located within 28.) Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 5, 6, & 12 are rejected under 35 U.S.C. 103 as being unpatentable over CHIDAMBARRAO in view of EKBOTE (US 20090050980 A1). Regarding Claim 5, CHIDAMBARRAO does not disclose: The semiconductor device of claim 1, wherein the nitrogen derivative impurities are located within the S/D region (26). EKBOTE discloses: nitrogen derivative impurities are located within the S/D region (Fig. 1: 150/160). (Par. 16 – 19 discloses ion implantation of nitrogen ions within the S/D region 150/160 for a similar MOSFET-type device, 100.) Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of CHIDAMBARRAO with those of EKBOTE such that the S/D region of the device of CHIDAMBARRAO comprises ion implanted nitrogen ions to enable the nitrogen derivative impurities to be located within the S/D region in CHIDAMBARRAO according to the teachings of EKBOTE for the further advantage of limiting undesired diffusion of the S/D dopants out of the S/D region, which aids in the miniaturization of such devices, EKBOTE Par. 19. Regarding Claim 6, CHIDAMBARRAO does not disclose: The semiconductor device of claim 1, wherein the nitrogen derivative impurities are located outside the anti-fuse doped region (28). EKBOTE discloses: the nitrogen derivative impurities are located outside the anti-fuse doped region (Fig. 1: 170). (Par. 16 – 19 discloses ion implantation of nitrogen ions within the S/D region 150/160—and, thus, outside of 170—for a similar MOSFET-type device, 100.) Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of CHIDAMBARRAO with those of EKBOTE such that the S/D region of the device of CHIDAMBARRAO comprises ion implanted nitrogen ions to enable the nitrogen derivative impurities to be located outside the anti-fuse doped region in CHIDAMBARRAO according to the teachings of EKBOTE for the further advantage of limiting undesired diffusion of the S/D dopants out of the S/D region, which aids in the miniaturization of such devices, EKBOTE Par. 19. Regarding Claim 12, CHIDAMBARRAO does not disclose: The semiconductor device of claim 11, wherein the nitrogen atoms are located within the S/D region (26).EKBOTE discloses: nitrogen atoms are located within the S/D region (Fig. 1: 150/160). (Par. 16 – 19 discloses ion implantation of nitrogen ions within the S/D region 150/160 for a similar MOSFET-type device, 100. And, nitrogen ions comprise nitrogen atoms.) Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of CHIDAMBARRAO with those of EKBOTE such that the S/D region of the device of CHIDAMBARRAO comprises ion implanted nitrogen ions to enable the nitrogen atoms to be located within the S/D region in CHIDAMBARRAO according to the teachings of EKBOTE for the further advantage of limiting undesired diffusion of the S/D dopants out of the S/D region, which aids in the miniaturization of such devices, EKBOTE Par. 19. Allowable Subject Matter Claims 2 is objected to as being dependent upon a rejected base claim but would be allowable if the base claim were rewritten to overcome its rejections under 35 U.S.C. 112(b) and Claims 2 were rewritten in independent form including all of the limitations of the amended base claim and any intervening claims. Claims 3 is objected to as being dependent upon a rejected base claim but would be allowable if the base claim were rewritten to overcome its rejections under 35 U.S.C. 112(b) and Claims 3 were rewritten in independent form including all of the limitations of the amended base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 2, The closest prior art to the claimed invention is CHIDAMBARRAO, which discloses a MOSFET-type anti-fuse device with nitrogen ions implanted into the device’s anti-fuse doped region. Further, CHIDAMBARRAO Par. 20 discloses that, after the nitrogen ions are implanted into the anti-fuse doped region, the “[anti-fuse medium] is then formed, as by local oxidation of silicon”—i.e. a “LOCOS” process, which mirrors Applicant’s disclosed method of forming the device. However, while it is conceivable that implanted nitrogen ions may form nitride compounds during a LOCOS process due to the elevated temperature during such a process, it is also conceivable that the conditions during the specific LOCOS process used for forming the device of CHIDAMBARRAO were deliberately not sufficient to form such compounds, as doing so is known to increase the resistance of the device, which CHIDAMBARRAO clearly finds undesirable in Par. 5 & 15. Regarding Claim 3, The closest prior art to the claimed invention is CHIDAMBARRAO, which discloses a MOSFET-type anti-fuse device with nitrogen ions implanted into the device’s anti-fuse doped region. Further, CHIDAMBARRAO Par. 20 discloses that, after the nitrogen ions are implanted into the anti-fuse doped region, the “[anti-fuse medium] is then formed, as by local oxidation of silicon”—i.e. a “LOCOS” process, which mirrors Applicant’s disclosed method of forming the device. However, while it is conceivable that implanted nitrogen ions may form oxynitride compounds during a LOCOS process due to the elevated temperature and the presence of an oxidizing agent during such a process, it is also conceivable that the conditions during the specific LOCOS process used for forming the device of CHIDAMBARRAO were deliberately not sufficient to form such compounds, as doing so is known to increase the resistance of the device, which CHIDAMBARRAO clearly finds undesirable in Par. 5 & 15. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST).. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K.S.S./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Nov 16, 2023
Application Filed
Jul 16, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
71%
Grant Probability
80%
With Interview (+8.3%)
3y 7m (~10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 7 resolved cases by this examiner. Grant probability derived from career allowance rate.

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