Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I (Claims 1-15 and 21-25) in the reply filed on 03/19/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 21-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Young et al. (US 2021/0408022).
As for claim 1, Young et al. disclose in Figs. 1-15 and the related text a method for manufacturing a semiconductor structure, comprising:
forming a first (left) patterned structure 92/90 on a memory region 200 of a base structure 50 and forming a second patterned structure 92 and a third patterned structure 92 on a logic region 300/400 of the base structure 50, the logic region 300/400 being displaced from the memory region 200 (Fig. 15), the first patterned structure 92 including a first patterned fin 90 and a first channel portion 54 disposed on and spaced apart from the first patterned fin 90, the second patterned structure 92 being displaced from the third patterned structure 300/400, the second patterned structure 300 including a second patterned fin 90 and a second channel portion 54 disposed on and spaced apart from the second patterned fin (fig. 3B, [0061]), the third patterned structure 92 including a third patterned fin 90 and a third channel portion 54 disposed on and spaced apart from the third patterned fin (fig. 3B, [0061]), each of the first channel portion, the second channel portion and the third channel portion having two exposed end surfaces which are opposite to each other (Fig. 5B and 15);
forming a patterned hard mask 94 covering the first patterned structure and the third patterned structure (Fig. 3A); and
performing an etching process through the patterned hard mask 94 so as to reduce a minimum distance between the two exposed end surfaces of the second channel portion (fig. 5A-5B and 15, [0023]).
As for claim 2, Young et al. disclose the method as claimed in claim 1, wherein the two exposed end surfaces of each of the first channel portion, the second channel portion and the third channel portion are opposite to each other in a first direction an (horizontal) direction (of Fig. 3B, also see fig. 15).
As for claim 3, Young et al. disclose the method as claimed in claim 2, wherein each of the first channel portion, the second channel portion and the third channel portion is spaced apart from a respective one of the first patterned fin (Fig. 15), the second patterned fin and the third patterned fin in a second direction different from the first direction [0061], each of the first channel portion, the second channel portion and the third channel portion has a width in a third direction different from the first direction and the second direction [0061], and the width of the second channel portion is greater than the width of each of the first channel portion and the third channel portion (Fig. 15).
As for claim 21, Young et al. disclose in Figs. 1-15 and the related text a method for manufacturing a semiconductor structure, comprising:
forming a first patterned structure (92 of 200) on a memory region of a base structure 50 and forming a second patterned structure (92 of 400) and a third patterned structure (92 of 300) on a logic region 300/400 of the base structure, the logic region being displaced from the memory region (Fig. 15), the first patterned structure including a first patterned fin 90 and a first channel portion 54 disposed on and spaced apart from the first patterned fin (Fig. 6A), the second patterned structure being displaced from the third patterned structure (fig. 15), the second patterned structure including a second patterned fin 90 and a second channel portion 54 disposed on and spaced apart from the second patterned fin (fig. 6A), the third patterned structure including a third patterned fin 90 and a third channel portion 54 disposed on and spaced apart from the third patterned fin (Fig. 6A), each of the first channel portion, the second channel portion and the third channel portion 54 having two end surfaces which are opposite to each other (fig. 3B-15);
forming a patterned hard mask 94 covering the first patterned structure and the third patterned structure (Fig. 3A, [0023]);
performing an etching process through the patterned hard mask 94 so as to reduce a minimum distance between the two end surfaces of the second channel portion [0023];
after removing the patterned hard mask, forming two first source/drain portions 112 so that the two first source/drain portions are respectively in contact with the two end surfaces of the first channel portion 54 (of 200, Fig. 7A, [0037]);
after the etching process, forming two second source/drain portions 112 so that the two second source/drain portions are respectively in contact with the two end surfaces of the second channel portion 54 (of 300/400, Fig. 7A); and
after removing the hard mask, forming two third source/drain portions so that the two third source/drain portions 112 are respectively in contact with the two end surfaces of the third channel portion 54 (of 400/300, fig. 7A).
As for claim 22, Young et al. disclose the method as claimed in claim 21, wherein the two end surfaces of each of the first channel portion, the second channel portion and the third channel portion are opposite to each other in a first (horizontal) direction (Fig. 7A).
As for claim 23, Young et al. disclose the method as claimed in claim 22, wherein the first channel portion, the second channel portion and the third channel portion 54 are respectively spaced apart from the first patterned fin, the second patterned fin and the third patterned fin 90 in a second (horizontal) direction different from the first direction (Fig. 6A), each of the first channel portion (54 of 200), the second channel portion (54 of 400) and the third channel portion (54 of 300) has a width in a third (diagonal) direction different from the first direction and the second direction (fig. 15), and the width of the second channel portion is greater than the width of each of the first channel portion and the third channel portion (fig. 15).
As for claim 24, Young et al. disclose the method as claimed in claim 23, wherein each of the two first source/drain portions 112 of 200, the two second source/drain portions (112 of 400) and the two third source/drain portions (112 of 300) includes a group IV semiconductor material, and is doped with group V impurities [0038].
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Young et al..
As for claim 25, Young et al. disclose the method as claimed in claim 23, wherein each of the two first source/drain portions 112 of 200, the two second source/drain portions (112 of 400) and the two third source/drain portions (112 of 300) includes a group IV semiconductor material [0038].
Young et al. do not disclose each of the two first source/drain portions, the two second source/drain portions and the two third source/drain portions is doped with group III impurities.
Since Young et al. teach the source/drain regions includes any material appropriate for N-type or P-type device.
Therefore, it is conventional and would have been obvious to one of ordinary skill in the art at the time the invention was made to provide each of the two first source/drain portions, the two second source/drain portions and the two third source/drain portions is doped with group III impurities, in order to provide suitable doping impurity.
Allowable Subject Matter
Claims 4-15 are allowed.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious “performing an etching process to selectively recess the two end surfaces of the channel portion in the second patterned structure without recessing the two end surfaces of the channel portion in the third patterned structure”, as recited in claim 4. Claims 5-15 depend among allowable claim 4.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TRANG Q TRAN/Primary Examiner, Art Unit 2811
Prosecution Insights