DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/08/2026 has been entered.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 11-17, and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Ooishi (US Pub. 2004/0062074) in view of Vaidyanath et al. (US Pub. 2012/0117338).
Regarding claims 1, 12, Fig. 14 of Ooishi discloses a memory device, comprising:
a plurality of first decoder lines [RA] disposed in a first metallization layer and extending in a first direction [horizontal];
wherein each of the first decoder lines [RA] includes at least a first segment [seg1] and a second segment [seg2] operatively coupled to a plurality of first memory cells [array1] and a plurality of second memory cells [array2], respectively; and
wherein the first segment [seg1] and second segment [seg2] of each of the first decoder lines [RA] are arranged side-by-side along the first direction [horizontal].
Ooishi discloses all claimed invention, but does not specifically disclose the first segment and the second segment of each of the first decoder are separate from each other along the first direction, while at least one of the first segment and the second segment is connected to at least one interconnect structure disposed vertically above the first and second segments and extending continuously across the first segment and the second segment. However, Fig. 2 of Vaidyanath discloses a first decoder lines including at least a first segment [CS-0] and a second segment [CS-1], that are separate from each other along the first direction, while at least one of the first segment and the second segment is connected to at least one interconnect structure [the structure comprises DEV1 to DV8 (DEV1 to DV8 can boxed together to make a interconnect structure), similar to a group of NOR gates that output WLPY0 to WLPY63] disposed vertically above the first and second segments [CS-0 and CS-1] and extending continuously across the first segment and the second segment [DEV1 to DEV8 extending continuously, just like WLPY0 to WLPY63].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Vaidyanath’s decoding lines to the teachings of Ooishi’s decoding line such that Ooishi decoding line are separate in two segments according to Vaidyanath’s teachings for the purpose of achieving independently access for each subset of memory [paragraphs 0011 and 0053].
Regarding claims 2, 14, and 22, Fig. 14 of Ooishi discloses a plurality of second decoder lines [col1, col2] disposed in a second metallization layer and extending in a second direction [vertical] perpendicular to the first direction [horizontal]; wherein the first segment [seg1] of each of the first decoder lines [RA] is operatively coupled to a first subset of the first memory cells [array1] through a first subset [col1] of the second decoder lines, and the corresponding second segment [seg2] of the first decoder line is operatively coupled to a first subset of the second memory cells [array2] through a second subset of the second decoder lines [col2].
Regarding claim 3, Fig. 14 of Ooishi discloses wherein the second metallization layer [where col1 and col2 are arranged] is disposed vertically below the first metallization layer [where RA are arranged].
Regarding claim 4, Fig. 14 of Ooishi discloses wherein the first subset [col1] of the second decoder lines and the second subset [col2] of the second decoder lines are spaced from each other [by COLUMN DECODER] with one or more other subsets of the second decoder lines [within COLUMN DECODER] along the first direction.
Regarding claim 5, Fig. 26 of Ooishi discloses a memory controller [6] configured to provide a plurality of decode signals to the plurality of first memory cells and the plurality of second memory cells through at least the first decoder lines [since decode signals are provided, a controller to provide the decode signal is inherent].
Regarding claim 6, Fig. 14 of Ooishi discloses wherein the memory controller [at the end where RA is labeled] is physically located next to the first segments [seg1], with the second segments [seg2] disposed opposite the first segments from the memory controller.
Regarding claims 7 and 15, Fig. 14 of Ooishi discloses a plurality of third decoder lines [BS] disposed in a third metallization layer [can be the same as first layer] and extending in the first direction [horizontal]; wherein each of the plurality of third decoder lines [BS] extends across the first and second segments [seg1, seg2] of a corresponding one of the plurality of first decoder lines.
Regarding claims 8, 16, and 23, Fig. 14 of Ooishi discloses wherein the third metallization layer is disposed vertically above the first metallization layer [BS is above RA].
Regarding claims 9 and 17, Fig. 14 of Ooishi discloses wherein each of the plurality of third decoder lines [BS] is only operatively coupled to the second segment [seg2] of the corresponding first decoder line [BS is corresponding to RA to select a row of a memory bank or array].
Regarding claim 11, Fig. 14 of Ooishi discloses a memory device, comprising:
a memory array including a plurality of first memory cells [array1] and a plurality of second memory cells [array2];
a memory controller [since control signals, RA, BS, RE, WE are provided, a controller is inherent] physically located next to the first memory cells [array1], with the second memory cells [array2] physically located opposite the first memory cells [array1] from the memory controller along a first direction [horizontal], wherein the memory controller is configured to provide a plurality of decode signals [RA, BS, RE, WE] to the memory array; and
a plurality of first decoder lines [RA] disposed in a first metallization layer and extending in the first direction [horizontal];
wherein each of the first decoder lines [RA] includes at least a first segment [seg1] and a second segment [seg2] operatively coupled to the first memory cells [array1] and the second memory cells [array2], respectively.
Ooishi discloses all claimed invention, but does not specifically disclose the first segment and the second segment of each of the first decoder are separate from each other along the first direction, while at least one of the first segment and the second segment is connected to at least one interconnect structure disposed vertically above the first and second segments and extending continuously across the first segment and the second segment. However, Fig. 2 of Vaidyanath discloses a first decoder lines including at least a first segment [CS-0] and a second segment [CS-1], that are separate from each other along the first direction, while at least one of the first segment and the second segment is connected to at least one interconnect structure [the structure comprises DEV1 to DV8 (DEV1 to DV8 can boxed together to make a interconnect structure), similar to a group of NOR gates that output WLPY0 to WLPY63] disposed vertically above the first and second segments [CS-0 and CS-1] and extending continuously across the first segment and the second segment [DEV1 to DEV8 extending continuously, just like WLPY0 to WLPY63].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Vaidyanath’s decoding lines to the teachings of Ooishi’s decoding line such that Ooishi decoding line are separate in two segments according to Vaidyanath’s teachings for the purpose of achieving independently access for each subset of memory [paragraphs 0011 and 0053].
Regarding claim 13, Fig. 14 of Ooishi discloses wherein a first subset [seg1] of the plurality of decode signals are [RA, BS, RE, WE] configured to activate the first memory cells [array1], and a second subset [seg2] of the plurality of decode signals are configured to activate the second memory cells [each segment can activate array1 and array2].
Regarding claim 21, Fig. 14 of Ooishi discloses a memory device a memory array including a plurality of first memory cells [array1] and a plurality of second memory cells [array2];
a memory controller physically [since control signals RA, BS, RE, WE are provided on the side of array1, a controller is inherent] located between the first memory cells [array1] and the second memory cells [array2] and configured to provide a plurality of decode signals [RA, BS, RE, WE, SE] to the memory array; and
a plurality of first decoder lines [RA] disposed in a first metallization layer and extending in a first direction [horizontal];
wherein each of the first decoder lines [RA] includes at least a first segment [seg1] and a second segment [seg2] operatively coupled to the first memory cells [array1] and the second memory cells [array2], respectively, and
wherein the first segment [seg1] and second segment [seg2] of each of the first decoder lines [RA] are arranged side-by-side along the first direction.
Ooishi discloses all claimed invention, but does not specifically disclose wherein the first segment and the second segment of each of the first decoder lines are arranged side-by-side along the first direction with a gap therebetween, while at least one of the first segment and the second segment is connected to at least one interconnect structure disposed vertically above the first and second segments and extending continuously across the first segment and the second segment. However, Fig. 2 of Ooishi discloses a gap [between VTT and 202] between the first segment [CS-0] and second segment [CS-1], while at least one of the first segment and the second segment is connected to at least one interconnect structure [the structure comprises DEV1 to DV8 (DEV1 to DV8 can boxed together to make a interconnect structure), similar to a group of NOR gates that output WLPY0 to WLPY63] disposed vertically above the first and second segments [CS-0 and CS-1] and extending continuously across the first segment and the second segment [DEV1 to DEV8 extending continuously, just like WLPY0 to WLPY63].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Vaidyanath’s decoding lines to the teachings of Ooishi’s decoding line such that Ooishi decoding line are separate in two segments according to Vaidyanath’s teachings for the purpose of achieving independently access for each subset of memory [paragraphs 0011 and 0053].
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ooishi (US Pub. 2004/0062074) in view of Vaidyanath et al. (US Pub. 2012/0117338) and further in view of Seok et al. (US Pub. 2023/0065980).
Regarding claim 10, Ooishi discloses all claimed invention, but does not specifically disclose wherein the plurality of first decoder lines each have a first width extending in a second direction perpendicular to the first direction and the plurality of third decoder lines each have a second width in the second direction, and wherein the second width is less than the first width. However, Fig. 1 of Seok discloses a memory device having plurality of signal lines, and the signal lines can have different width [paragraph 0007, last sentence].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Seok’s memory device to the teachings of Ooishi such that Ooishi memory device can have different signal lines with different widths according to Seok’s teachings for the purpose of having different drivability for different signals to improve decoding operation.
Response to Arguments
Applicant's arguments filed 04/29/2026 have been fully considered but they are not persuasive. while at least one of the first segment and the second segment is connected to at least one interconnect structure disposed vertically above the first and second segments and extending continuously across the first segment and the second segment. Applicant pointed to Fig. 2 of the application for support of the amendment. As shows in Fig. 2, the interconnect structure is the box 270, which comprises plurality of NOR gates that output WLPY0 to WLPY63. Each NOR gate does not extending across the first segment and second segments. However, the plurality of NOR gates does extending (one after another) across the first and second segment. Similar to Fig. 2 of Vaidyanath, at least one of the first segment and the second segment is connected to at least one interconnect structure [the structure comprises DEV1 to DV8 (DEV1 to DV8 can boxed together to make a interconnect structure), similar to a group of NOR gates that output WLPY0 to WLPY63] disposed vertically above the first and second segments [CS-0 and CS-1] and extending continuously across the first segment and the second segment [DEV1 to DEV8 extending continuously, just like WLPY0 to WLPY63].
Therefore, all applicant’s arguments were fully considered, they are not persuasive.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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