DETAILED ACTION
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Election/Restrictions
Applicant’s election without traverse of species A/fig. 1-3, reflected in claims 1-20 in the reply filed on 06/08/2026 is acknowledged.
But claims 3 and 18 include feature ‘second gate structure is electrically coupled to the second drain feature’ and claim 14 includes feature “wherein the fourth gate structure is electrically coupled to the fourth drain feature” is shown in species B/fig. 4, different than elected species A/fig. 1. Thus, claims 3, 14 and 18 will be considered as withdrawn.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Worley (US 20080259511 A1, hereinafter Worley’511).
Regarding independent claim 1, Worley’511 teaches, “A semiconductor structure (100, fig. 1-16; ¶ [0001] - ¶ [0043]), comprising:
a first transistor (NFET 104, fig. 7) comprising:
a first source feature (see annotation),
a first drain feature (see annotation), and
a first gate structure (see annotation); and
a second transistor (NFET 105) comprising:
a second source feature (see annotation),
a second drain feature (see annotation), and
a second gate structure (see annotation),
wherein the first source feature is electrically coupled to the second source feature,
wherein the second drain feature is electrically coupled to the first gate structure”.
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Regarding claim 2, Worley’511 further teaches, “The semiconductor structure of claim 1, wherein the second gate structure is electrically coupled to the second source feature (fig. 7)”.
Claims 9 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chu et al. (US 10510742 B1, hereinafter Chu’742).
Regarding independent claim 9, Chu’742 teaches, “A semiconductor structure (fig. 1-6; related description), comprising:
a substrate (201);
a first well region (290) and a second well region (202) on the substrate (201);
a first transistor (see annotation) and a second transistor (see annotation) disposed over the first well region (290); and
a third transistor (see annotation) and a fourth transistor (see annotation) disposed over the second well region,
wherein the first transistor comprises a first source feature (231), a first drain feature (232), and a first gate structure,
wherein the second transistor comprises a second source feature (221), a second drain feature (222), and a second gate structure,
wherein the third transistor comprises a third source feature (251), a third drain feature (252), and a third gate structure,
wherein the fourth transistor comprises a fourth source feature (262), a fourth drain feature (261), and a fourth gate structure,
wherein the first source feature (231) is electrically coupled to the fourth source feature (262),
wherein the first gate structure is electrically coupled (by 270) to the fourth drain feature (261)”.
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Regarding claim 13, Chu’742 further teaches, “The semiconductor structure of claim 9, wherein the fourth gate structure is electrically (not directly) coupled to the fourth source feature”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Worley’511 as applied to claim 1 as above, and further in view of Park et al. (US 20200203335 A1, hereinafter Park’005).
Regarding claim 7, Worley’511 teaches all the limitations described in claim 1.
But Worley’511 is silent upon the provision of wherein the semiconductor structure of claim 1, further comprising: a bottom dielectric layer, wherein the first transistor and the second transistor are disposed on the bottom dielectric layer.
However, Park’005 teaches a similar device wherein the substrate (101) is a SOI substrate. SOI substrate includes a dielectric layer between a bulk substrate and a silicon layer.
Worley’511 and Park’005 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Worley’511 with the features of Park’005 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Worley’511 and Park’005 to include a SOI substrate according to the teachings of Park’005 with a motivation of exploiting the advantages of the SOI substrate e.g., faster switching speeds, lower power consumption, complete elimination of latch-up, and better radio-frequency (RF) signal isolation etc.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Worley’511 as applied to claim 1 as above, and further in view of Huang et al. (US 11158634 B1, hereinafter Huang’634).
Regarding claim 8, Worley’511 teaches all the limitations described in claim 1.
But Worley’511 is silent upon the provision of wherein the first transistor further comprises a plurality of nanostructures extending between the first source feature and the first drain feature, wherein the first gate structure wraps around each of the plurality of nanostructures.
However, Huang’634 teaches a gate-all-around (GAA) transistor (fig. 1), comprises a plurality of nanostructures extending between the first source feature and the first drain feature, wherein the first gate structure wraps around each of the plurality of nanostructures.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Worley’511 and Huang’634 to use a gate-all-around (GAA) transistor according to the teachings of Huang’634 with a general motivation of exploiting the advantages of the gate-all-around (GAA) transistor e.g., superior electrostatic control, high yield, low power and low electrical current leakage etc.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chu’742 as applied to claim 9 as above, and further in view of Huang’634.
Regarding claim 15, Chu’742 teaches all the limitations described in claim 9.
But Chu’742 is silent upon the provision of wherein the first transistor further comprises a plurality of nanostructures extending between the first source feature and the first drain feature, wherein the first gate structure wraps around each of the plurality of nanostructures.
However, Huang’634 teaches a gate-all-around (GAA) transistor (fig. 1), comprises a plurality of nanostructures extending between the first source feature and the first drain feature, wherein the first gate structure wraps around each of the plurality of nanostructures.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Chu’742 and Huang’634 to use a gate-all-around (GAA) transistor according to the teachings of Huang’634 with a general motivation of exploiting the advantages of the gate-all-around (GAA) transistor e.g., superior electrostatic control, high yield, low power and low electrical current leakage etc.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Chu’742 in view of Park’005.
Regarding independent claim 16, Chu’742 teaches, “A semiconductor structure (fig. 1-6; related description), comprising:
((a dielectric layer;))
a first well region (290) and a second well region (202) ((over the dielectric layer));
a first transistor (see annotation) disposed over the first well region (290); and
a second transistor (see annotation) disposed over the second well region (264);
wherein the first transistor comprises a first source feature (231), a first drain feature (232), and a first gate structure,
wherein the second transistor (see annotation) comprises a second source feature (262), a second drain feature (261), and a second gate structure,
wherein the first source feature (231) is electrically coupled to the second source feature (262),
wherein the first gate structure is electrically coupled to the second drain feature (261)”.
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But Chu’742 is silent upon the provision of wherein the semiconductor structure comprising a dielectric layer and the first and second well regions are over the dielectric layer.
However, Park’005 teaches a similar device wherein the substrate (101) is a SOI substrate. SOI substrate includes a dielectric layer between a bulk substrate and a silicon layer.
Chu’742 and Park’005 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chu’742 with the features of Park’005 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Chu’742 and Park’005 to include a SOI substrate according to the teachings of Park’005 with a motivation of exploiting the advantages of the SOI substrate e.g., faster switching speeds, lower power consumption, complete elimination of latch-up, and better radio-frequency (RF) signal isolation etc.
Regarding claim 17, Chu’742 further teaches, “The semiconductor structure of claim 16, wherein the second gate structure is electrically coupled to the second source feature.”
Allowable Subject Matter
Claims 4-6, 10-12 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding dependent claim 4, the prior arts of record do not anticipate or make obvious, inter alia, the feature of: wherein the first transistor is disposed on a first doped well on a substrate, wherein each the first source feature and the first drain feature is insulated from the first doped well by a first isolation layer.
Regarding dependent claim 10, the prior arts of record do not anticipate or make obvious, inter alia, the feature of: wherein the second source feature, the second drain feature, the third source feature, and the third drain feature are electrically floating.
Regarding dependent claim 11, the prior arts of record do not anticipate or make obvious, inter alia, the feature of: wherein the second transistor is not electrically coupled to the third transistor.
Regarding dependent claim 12, the prior arts of record do not anticipate or make obvious, inter alia, the feature of: wherein the first source feature, the first drain feature, the second source feature, and the second drain feature are insulated from the first well region, wherein the third source feature, the third drain feature, the fourth source feature, and the fourth drain feature are insulated from the second well region.
Regarding dependent claim 19, the prior arts of record do not anticipate or make obvious, inter alia, the feature of: a third well region and a fourth well region over the dielectric layer; a third transistor disposed over the third well region; and a fourth transistor disposed over the fourth well region, wherein the first well region, the second well region, the third well region, and the fourth well region are insulated from one another, wherein the third transistor and fourth transistor are not electrically connected.
Claims 5-6 and 20 are also objected as they depend on objected claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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