DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 4, 6-11, 13-22, and 24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Norfidathul et al, US Patent Application Publication 2008/0170391.
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Regarding claim 1, teaches a light-emitting diode (LED) package comprising:
a first LED chip 102;
a second LED chip 103;
a third LED chip 104;
a housing (as labeled in figure above); and
a lead frame structure at least partially within the housing and electrically coupled to the first LED chip, the second LED chip, and the third LED chip, the lead frame structure comprising:
a first lead 109/108/106 electrically connected to the first LED chip 109, the second LED chip, and the third LED chip, the first lead comprising multiple pins 106, 108 that extend out of a first edge the housing, the first lead extending from the first edge and past a center line of the housing;
a second lead 106 electrically connected to the first LED chip; and
a third lead 107 electrically connected to the second LED chip; and
a fourth lead 108 electrically connected to the third LED chip;
wherein the center line is positioned between and parallel to the first edge and an opposing edge of the housing where the second lead, the third lead, and the fourth lead exit the housing (figure 9).
Regarding claims 3 and 4, Norfidathul teaches the first lead forms a common anode connection for the first LED chip, the second LED chip, and the third LED chip and the first lead forms a common cathode connection for the first LED chip, the second LED chip, and the third LED chip (figure 9).
Regarding claim 6, Norfidathul teaches a surface of the multiple pins (61and 64) defines a package mounting surface in a first plane (which is shown in 6); surfaces of the first lead and second lead define LED chip mounting surfaces in a second plane (shown in figure 9, which has surfaces upon which LED chips may be mounted); and an intermediate portion of the lead frame structure extends between the first plane and the second plane (as shown in figure 4, wherein the pins are shown as clips with a top surface, bottom surface, and a side portion that connects the top and bottom).
Regarding claim 7, Norfidathul teaches the housing forms a recess in which the first LED chip, the second LED chip, and the third LED chip reside (figure 8).
Regarding claims 8-9, Norfidathul teaches a light collector (sidewalls of 97 in figure 8) within the recess and over the first LED chip, the second LED chip, and the third LED chip, the light collector forming an aperture configured to pass light from the first LED chip, the second LED chip, and the third LED chip, wherein a fill material 91 within the recess and covering portions of the light collector (figure 8).
Regarding claim 10, Norfidathul teaches the housing forms a first recess in which the first LED chip resides, a second recess in which the second LED chip resides, and third recess in which the third LED chip resides (wherein the first, second, and third recesses are all the same recess in figures 5 and 9).
Regarding claim 11, Norfidathul teaches the first LED chip, the second LED chip, and the third LED chip are mounted on and thermally coupled with the first lead (figure 9).
Regarding claim 13, Norfidathul teaches a fourth LED chip 105, wherein the first lead is a common electrode for the first LED chip, the second LED chip, the third LED chip, and the fourth LED chip (figure 9).
Regarding claim 14, Norfidathul teaches a light-emitting diode (LED) package comprising:
a housing (as labeled in figure above)
a first LED chip 101;
a second LED chip 102; and
a lead frame structure with a first lead, the first lead 109 forming a common electrode for the first LED chip and the second LED chip, the first lead comprising multiple pins 106/107/108 (right side) that extend from a same side of the housing including a first pin that extends out of a first edge of the housing and a second pin 106/108 (left side) that extends out of an opposing edge of the housing, the multiple pins being configured to receive external electrical connections to the common electrode (figure 9).
Regarding claims 15-16, Norfidathul teaches the common electrode is a common anode connection for the first LED chip and the second LED chip and the common electrode is a common cathode connection for the first LED chip and the second LED chip (figure 9).
Regarding claim 17, Norfidathul teaches a surface of the multiple pins defines a package mounting surface in a first plane (which is shown in 6); a surface of the first lead defines an LED chip mounting surface in a second plane (shown in figure 9, which has surfaces upon which LED chips may be mounted); and an intermediate portion of the lead frame structure extends between the first plane and the second plane (as shown in figure 4, wherein the pins are shown as clips with a top surface, bottom surface, and a side portion that connects the top and bottom).
Regarding claim 18, Norfidathul teaches the housing forms a recess in which the first LED chip and the second LED chip reside (figure 8).
Regarding claims 19-20, Norfidathul teaches a light collector (sidewalls of 97 in figure 8) within the recess and over the first LED chip and the second LED chip, the light collector forming an aperture configured to pass light from the first LED chip and the second LED chip, further comprising a fill material 91 within the recess and covering portions of the light collector (figure 8).
Regarding claim 21, Norfidathul teaches the housing forms a first recess in which the first LED chip resides and a second recess in which the second LED chip resides (wherein the first, second, and third recesses are all the same recess in figures 5 and 9).
Regarding claim 22, Norfidathul teaches a third LED chip, wherein the first lead is the common electrode for the first LED chip, the second LED chip, and the third LED chip (figure 9).
Regarding claim 24, Norfidathul the first LED chip and the second LED chip are mounted on and thermally coupled with the first lead (figure 9).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Norfidathul as applied to claims 1 and 14 above, and further in view of Wu et al, US Patent Application Publication 2015/0380607.
Regarding claims 12, Norfidathul fails to teach the first LED chip is further mounted on and thermally coupled with the second lead; the second LED chip is further mounted on and thermally coupled with the third lead; and the third LED chip is further mounted on and thermally coupled with the fourth lead of the lead frame structure.
However, Wu teaches an alternative, yet generally-known means of connecting LED chips to lead frame pins without the use of wires. This involves the LED chip 730B, 730G being bonded to two different lead frame pins 720B1, 720C1, 720G1 as shown in figure 6. Combining this teaches of Wu with that of Norfidathul meets the limitation of “…the first LED chip is further mounted on and thermally coupled with the second lead; the second LED chip is further mounted on and thermally coupled with the third lead; and the third LED chip is further mounted on and thermally coupled with the fourth lead of the lead frame structure”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wu with that of Norfidathul because flip-chip wirebonding is an alternative, yet generally-known means of connecting LED chips to lead frame pins without the use of wires, and is a more secure means of electrically connecting the LED chips to the frame.
Regarding claim 23, while Norfidathul teaches the lead frame structure further comprises a second lead and a third lead (which would be 106, 107 or 108); Norfidathul fails to teach the first LED chip is flip-chip mounted between the first lead and the second lead; and the second LED chip is flip-chip mounted between the first lead and the third lead.
However, Wu teaches an alternative, yet generally-known means of connecting LED chips to lead frame pins without the use of wirebonding. This involves the LED chip 730B, 730G being bonded to two different lead frame pins 720B1, 720C1, 720G1 as shown in figure 6. Combining this teaches of Wu with that of Norfidathul meets the limitation of “…the first LED chip is flip-chip mounted between the first lead and the second lead; and the second LED chip is flip-chip mounted between the first lead and the third lead. ”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wu with that of Norfidathul because flip-chip wirebonding is an alternative, yet generally-known means of connecting LED chips to lead frame pins without the use of wires, and is a more secure means of electrically connecting the LED chips to the frame.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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QVJ
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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