DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-11, 14-22, and 24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al, US Patent Application Publication 2020/0041111
Regarding claim 1, Lin teaches a light-emitting diode (LED) package comprising:
a first LED chip (left); a second LED chip (center); a third LED chip (right, all of which are labeled 4);
a housing 1; and
a lead frame structure 2, 3 at least partially within the housing and electrically coupled to the first LED chip, the second LED chip, and the third LED chip, the lead frame structure comprising:
a first lead 21 (which is part of lead structure 2) electrically connected to the first LED chip, the second LED chip, and the third LED chip, the first lead comprising multiple pins 22 (figures 7 and 9) that extend out of the housing;
a second lead electrically connected to the first LED chip (left portion of 321 in figure 9, in which LED chip 4 and 321 are electrically connected together via chip 5); and
a third lead electrically connected to the second LED chip (which is either 311 or 322 in figure 9, which LED chip 4 and 311 or 322 are electrically connected together via chip 5. See also figure 3).
Regarding claim 2, Lin teaches the multiple pins of the first lead extend out of a same side of the housing (figures 7 and 9).
Regarding claims 3 and 4, Lin teaches the first lead forms a common anode connection for the first LED chip, the second LED chip, and the third LED chip and the first lead forms a common cathode connection for the first LED chip, the second LED chip, and the third LED chip (figures 7 and 9).
Regarding claim 5, Lin teaches the first lead extends from a first edge of the housing (as shown in figure 9) and past a center line of the housing (as shown in figure 3 below).
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Regarding claim 6, Lin teaches a surface of the multiple pins defines a package mounting surface in a first plane; surfaces of the first lead and second lead define LED chip mounting surfaces in a second plane; and an intermediate portion of the lead frame structure extends between the first plane and the second plane (figure 7, as shown in figure below).
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Regarding claim 7, Lin teaches the housing forms a recess in which the first LED chip, the second LED chip, and the third LED chip reside (as shown in figure 3).
Regarding claims 8 and 9, Lin teaches a light collector within the recess and over the first LED chip, the second LED chip, and the third LED chip, the light collector forming an aperture configured to pass light from the first LED chip, the second LED chip, and the third LED chip (with the light collector being the sidewalls 111 of the housing 1 in figure 3), wherein a fill material 6 within the recess and covering portions of the light collector (figure 3).
Regarding claim 10, Lin teaches the housing forms a first recess in which the first LED chip resides, a second recess in which the second LED chip resides, and third recess in which the third LED chip resides (wherein the first, second, and third recess are all of the same recess in figure 3).
Regarding claim 11, Lin teaches the first LED chip, the second LED chip, and the third LED chip are mounted on and thermally coupled with the first lead (figures 3, 7, and 9).
Regarding claim 14 , Lin teaches a light-emitting diode (LED) package comprising:
a housing 1;
a first LED chip 4 (left); a second LED chip 4 (middle or right); and
a lead frame structure with a first lead, the first lead forming a common electrode 21 for the first LED chip and the second LED chip, the first lead comprising multiple pins 22 (figures 7 and 9) that extend from a same side of the housing, the multiple pins being configured to receive external electrical connections to the common electrode (figures 3, 7, and 9).
Regarding claims 15 and 16, Lin teaches the common electrode is a common anode connection for the first LED chip and the second LED chip and the common electrode is a common cathode connection for the first LED chip and the second LED chip (figures 7 and 9).
Regarding claim 17, Lin teaches a surface of the multiple pins defines a package mounting surface in a first plane; a surface of the first lead defines an LED chip mounting surface in a second plane; and an intermediate portion of the lead frame structure extends between the first plane and the second plane (as shown in figure above).
Regarding claim 18, Lin teaches the housing forms a recess in which the first LED chip and the second LED chip reside (as shown in figure 3).
Regarding claims 19-20, Lin teaches a light collector within the recess and over the first LED chip and the second LED chip, the light collector forming an aperture configured to pass light from the first LED chip and the second LED chip (with the light collector being the sidewalls 111 of the housing 1 in figure 3), wherein a fill material 6 within the recess and covering portions of the light collector (figure 3).
Regarding claim 21, Lin teaches the housing forms a first recess in which the first LED chip resides and a second recess in which the second LED chip resides (wherein the first and second recess are all of the same recess in figure 3).
Regarding claim 22, Lin teaches a third LED chip 4 (other one of middle or right), wherein the first lead is the common electrode for the first LED chip, the second LED chip, and the third LED chip (figures 3, 7, and 9)
Regarding claim 24, Lin teaches the first LED chip and the second LED chip are mounted on and thermally coupled with the first lead (figures 3, 7, and 9)
Claim(s) 1-5, 11-16, and 22-24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al, US Patent Application Publication 2015/0380607
Regarding claim 1, Wu teaches a light-emitting diode (LED) package comprising:
a first LED chip 730R’; a second LED chip 730G; a third LED chip 730B;
a housing 710; and
a lead frame structure 720C1, 720R1, 720B1, 720G1 at least partially within the housing and electrically coupled to the first LED chip, the second LED chip, and the third LED chip, the lead frame structure comprising:
a first lead 720C1 electrically connected to the first LED chip, the second LED chip, and the third LED chip, the first lead comprising multiple pins 720C2 that extend out of the housing;
a second lead 720R1 electrically connected to the first LED chip; and
a third lead 720G1 electrically connected to the second LED chip (figures 8 and 9).
Regarding claim 2, Wu teaches the multiple pins of the first lead extend out of a same side of the housing (which is the bottom side of figure 9).
Regarding claims 3 and 4, Wu teaches the first lead forms a common anode connection for the first LED chip, the second LED chip, and the third LED chip and the first lead forms a common cathode connection for the first LED chip, the second LED chip, and the third LED chip (figures 8-9).
Regarding claim 5, Wu teaches the first lead extends from a first edge of the housing and past a center line of the housing (which is shown as line e’-e’ in figure 8).
Regarding claim 11, Wu teaches the first LED chip, the second LED chip, and the third LED chip are mounted on and thermally coupled with the first lead (figures 8-9)
Regarding claim 12, Wu teaches the first LED chip is further mounted on and thermally coupled with the second lead 720R1; the second LED chip is further mounted on and thermally coupled with the third lead 720G1; and the third LED chip is further mounted on and thermally coupled with a fourth lead 720R1 of the lead frame structure (as shown in figure 8).
Regarding claim 13, Wu teaches a fourth LED chip 730B, wherein the first lead is a common electrode for the first LED chip, the second LED chip, the third LED chip, and the fourth LED chip (figure 8)
Regarding claim 14 , Wu teaches a light-emitting diode (LED) package comprising:
a housing 710 (figure 9)`;
a first LED chip 730R’; a second LED chip 730G; and
a lead frame structure with a first lead, the first lead forming a common electrode 720C1 for the first LED chip and the second LED chip, the first lead comprising multiple pins 720C2 that extend from a same side of the housing, the multiple pins being configured to receive external electrical connections to the common electrode (figures 8-9).
Regarding claims 15 and 16, Wu teaches the common electrode is a common anode connection for the first LED chip and the second LED chip and the common electrode is a common cathode connection for the first LED chip and the second LED chip (figures 8-9).
Regarding claim 22, Wu teaches a third LED chip 720R’ wherein the first lead is the common electrode for the first LED chip, the second LED chip, and the third LED chip (figures 8-9)
Regarding claim 23, Wu teaches the lead frame structure further comprises a second lead 720R1 and a third lead 720G1; the first LED chip is flip-chip mounted between the first lead and the second lead; and the second LED chip is flip-chip mounted between the first lead and the third lead (Figures 8-9).
Regarding claim 24, Wu teaches the first LED chip and the second LED chip are mounted on and thermally coupled with the first lead (figures 8-9)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. The examiner can normally be reached M-F 7AM-4PM.
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QVJ
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899