DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 & 7-8 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al. (US 20230099156).
Regarding claim 1, Chen discloses that a method, comprising:
forming a first semiconductor stack 22 & 21 on a first substrate 10 (Fig. 2A);
forming a second semiconductor stack 25-26 on a second substrate 11 (Fig. 2B);
bonding the second substrate to the first substrate so that the second semiconductor stack is stacked over the first semiconductor stack (Fig. 4);
removing the second substrate (para. 0059, note: “ - -semiconductor substrate can be removed - -“ ); and
patterning the first semiconductor stack and the second semiconductor stack to form a fin structure (Fig. 8A); and
forming a first transistor and a second transistor from the fin structure, wherein the first transistor (a bottom transistor) comprises first source/drain regions 92 disposed across a portion of the first semiconductor stack, and the second transistor (a top transistor) comprises second source/drain regions 94 disposed across a portion of the second semiconductor stack (Fig. 9A & 10A).
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Reclaim 2, Chen discloses that depositing a first dielectric layer 31 over the first semiconductor stack; and
depositing a second dielectric layer 62 formed over the second semiconductor stack, wherein bonding the second substrate to the first substrate comprises bonding the first dielectric layer to the second dielectric layer (Fig. 6A).
Reclaim 3, Chen discloses that forming the first semiconductor stack comprises:
alternately depositing two or more first semiconductor layers 22 and two or more second semiconductor layers 21 (Fig. 2A).
Reclaim 7, Chen discloses that the first substrate has a first crystalline orientation, and the second substrate has a second crystalline orientation different from the first crystalline orientation (para. 0060, note: 21 & 22 has a [100] and 25-26 has a [110]).
Reclaim 8, Chen discloses that aligning the first and second substrate according to the first and second crystalline orientation prior to bonding the first and second substrate (Fig. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20230099156) in view of Bao et al. (US 20230197721).
Reclaim 4, Chen fails to specify that depositing an etch stop layer on the first semiconductor stack prior to depositing the first dielectric layer 128 (Fig. 2B).
However, Bao suggests that an etch stop layer 126 on the first semiconductor stack prior to depositing the first dielectric layer 128.
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Chen with depositing an etch stop layer on the first semiconductor stack prior to depositing the first dielectric layer as taught by Bao in order to enhance extra protection on the semiconductor device and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Reclaim 5, Che & Bao disclose that the etch stop layer comprises a dielectric material 126 (para. 0065, note: the insulator layer).
Reclaim 6, Che & Bao disclose that the etch stop layer comprises a semiconductor material (para. 0065).
Claim(s) 9-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bao et al. (US 20230197721) in view of Chung et al. (US 20210265349).
Regarding claim 9, Bao discloses that a method, comprising:
forming a fin structure 114 over a first substrate 116, wherein the fin structure comprises:
a first semiconductor channel layer 120having a first crystalline orientation;
a second semiconductor channel layer 506 having a second crystalline orientation (para. 0063); and
a bonding structure 126, 128, 124 between the first semiconductor channel layer and second semiconductor channel layer;
etching the fin structure (below element 128) on opposite sides of the fin structure;
forming first source/drain regions in contact with the first semiconductor channel layer;
forming second source/drain regions in contact with the second semiconductor channel layer (Fig. 2B).
Bao fails to teach that forming a sacrificial gate structure over the fin structure and depositing a first CESL (contact etch stop layer) over the first source/drain regions;
depositing a first ILD (interlayer dielectric) layer on the first CESL;
forming second source/drain regions in contact with the second semiconductor channel layer;
depositing a second CSEL over the second source/drain regions; and depositing a second ILD layer on the second CESL.
However, Chung suggests that a sacrificial gate structure 216 over the fin structure and depositing a first CESL 234 (contact etch stop layer) over the first source/drain regions 232 (Fig. 16);
depositing a first ILD (interlayer dielectric) layer 236 on the first CESL 234 (Fig. 21);
depositing a second CSEL over the second source/drain regions; and
depositing a second ILD layer on the second CESL (repeating process).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Bao with depositing a first ILD (interlayer dielectric) layer on the first CESL; forming second source/drain regions in contact with the second semiconductor channel layer; depositing a second CSEL over the second source/drain regions; and depositing a second ILD layer on the second CESL as taught by Chung in order to enhance complexity of semiconductor devices with properly isolate source and drain and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Reclaim 10, Bao & Chung disclose that forming the fin structure comprising:
depositing the first semiconductor channel layer 114 on the first substrate 116, wherein the first substrate has the first crystalline orientation (Bao, para. 0053);
depositing a first bonding layer 128 over the first semiconductor channel layer 114 (Bao, Fig. 1B-1F);
forming the second semiconductor channel layer 104 on a second substrate 106 having the second crystalline orientation (Bao, para. 0053);
depositing a second bonding layer 124 over the second semiconductor channel layer; and bonding the first and second bonding layers to form the bonding structure (Bao, Fig. 1F).
Reclaim 11, Bao & Chung disclose that prior to bonding the first and second bonding layers, aligning the first and second substrates according to the first and second crystalline orientations (Bao, Fig. 0053, Fig. 1B-1F).
Reclaim 12, Bao & Chung disclose that the first bonding layer comprises a dielectric layer (Bao, insulator layer).
Reclaim 13, Bao & Chung disclose that depositing an etch stop layer 126 over the first semiconductor channel layer, wherein the first bonding layer is deposited on the etch stop layer (Fig. 1F, Bao).
Reclaim 14, Bao & Chung disclose that the etch stop layer comprises a dielectric material (Fig. 8B).
Reclaim 15, Bao & Chung disclose that the etch stop layer comprises silicon (para. 0065).
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20230420460) in view of Bao et al. (US 20230197721).
Regarding claim 16, Huang discloses that a semiconductor device, comprising:
a first channel layer 130b (Fig. 1A);
a first gate dielectric layer 120 (para. 0065) surrounding the first channel layer 130 (note: around channel 103b, Fig. 1A);
a first gate electrode layer 122 disposed on the first gate dielectric layer 120;
first source/drain regions 150d in contact with the first channel layer 130b (Fig. 3C1);
a second channel layer 103a disposed below and aligned with the first channel layer 103b (Fig. 3C1);
a second gate dielectric layer 120 surrounding the second channel layer 103a;
a second gate electrode layer 122 disposed on the second gate dielectric layer 120;
second source/drain regions 150b in contact with the second channel layer 130a; and
Huang fails to teach that a bonding structure disposed between the first channel layer and the second channel layer and aligned with the first and second channel layers.
However, Bao suggests that a bonding structure 128 disposed between the first channel layer and the second channel layer and aligned with the first and second channel layers (Fig. 2B).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Huang with a bonding structure disposed between the first channel layer and the second channel layer and aligned with the first and second channel layers as taught by Bao in order to high-quality N/P junction isolation (para. 0050) and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Reclaim 17, Huang & Bao discloses that the bonding structure comprises: a first dielectric bonding layer 126; and a second dielectric bonding layer 128 bonded to the first dielectric bonding layer 126 by a dielectric-to-dielectric direct bonding (Bao, Fig. 2B).
Reclaim 17, Huang & Bao discloses that the first channel layer has a first crystalline orientation, and the second channel layer has a second crystalline orientation.
Reclaim 19, Huang & Bao discloses that the bonding structure further comprises: a third dielectric layer 126 facing the first channel layer 120; and a fourth dielectric layer 128 facing the second channel layer 110 (Bao, Fig. 2B).
Reclaim 20, Huang & Bao discloses that the first channel layer has a first crystalline orientation, and the second channel layer has a second crystalline orientation (Huang, para. 0029).
Conclusion
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/SU C KIM/ Primary Examiner, Art Unit 2899