Prosecution Insights
Last updated: October 04, 2026
Application No. 18/512,371

VERTICALLY STACKED COMPLEMENTARY FIELD EFFECT TRANSISTORS AND METHODS OF FABRICATION THEREOF

Non-Final OA §103
Filed
Nov 17, 2023
Examiner
KIM, SU C
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Non-Final)
78%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
66%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
718 granted / 923 resolved
+9.8% vs TC avg
Minimal -12% lift
Without
With
+-11.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
35 currently pending
Career history
962
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
59.5%
+19.5% vs TC avg
§102
23.8%
-16.2% vs TC avg
§112
6.4%
-33.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 923 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 16-18 & 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 20230099156 ) in view of Gardner et al. (US 20220238520). Regarding claim 16, Cheng disclose that a semiconductor device, comprising: a first channel layer 26; a first gate dielectric layer (para. 0080) surrounding the first channel layer 26 (Fig. 10A); a first gate electrode layer disposed on the first gate dielectric layer (para. 0080); first source/drain regions 94 in contact with the first channel layer 26; a second channel layer 22 disposed below and aligned with the first channel layer 26; a second gate dielectric layer 93 (para. 0080) surrounding the second channel layer 22; a second gate electrode layer 93 (para. 0080) disposed on the second gate dielectric layer; second source/drain regions 92 in contact with the second channel layer 22; a bonding structure 31 disposed between the first channel layer 26 and the second channel layer 22 and aligned with the first and second channel layers (Fig. 10A). Cheng fails to teach that a first contact etch stop layer (CESL) disposed on the first source/drain regions; a first interlayer dielectric (ILD) layer disposed on the first CESL and a second CESL disposed on the second source/drain regions; a second ILD layer disposed on the second CESL, wherein the second ILD layer is in contact with the first source/drain regions and the first CESL. However, Gardner suggests that a first contact etch stop layer (CESL) 2321 disposed on the first source/drain regions 2320; a first interlayer dielectric (ILD) layer 2440 disposed on the first CESL 2321 and a second CESL 2421 disposed on the second source/drain regions 2420; a second ILD layer 2340 (Fig. 23 & 24, a bottom layer of an element 2340 and a top layer of the element 2340) disposed on the second CESL, wherein the second ILD layer 2340 (a top layer) is in contact with the first source/drain regions and the first CESL (Fig. 23-25). Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Cheng with a first contact etch stop layer (CESL) disposed on the first source/drain regions; a first interlayer dielectric (ILD) layer disposed on the first CESL and a second CESL disposed on the second source/drain regions; a second ILD layer disposed on the second CESL, wherein the second ILD layer is in contact with the first source/drain regions and the first CESL. as taught by Gardner in order to enhance electrical separation from the first and second source/drain and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art. Reclaim 17, Cheng & Gardner disclose that the bonding structure comprises: a first dielectric bonding layer 1810; and a second dielectric bonding layer 1880 bonded to the first dielectric bonding layer 1870 by a dielectric-to-dielectric direct bonding (Gardner, Fig. 25). Reclaim 17, Cheng & Gardner disclose the first channel layer has a first crystalline orientation, and the second channel layer has a second crystalline orientation (Cheng’s Fig. 10A in view of Gardner’s Fig. 25). Reclaim 21, Cheng & Gardner disclose the bonding structure is in contact with the second CESL (thermally contact). Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 20230099156 ) in view of Gardner et al. (US 20220238520) and further in view of Bao et al. (US 20230197721). Reclaim 19, Cheng & Gardner fail to teach that the bonding structure further comprises: a third dielectric layer facing the first channel layer; and a fourth dielectric layer facing the second channel layer. Bao suggests that that the bonding structure further comprises: a third dielectric layer 126 facing the first channel layer 120; and a fourth dielectric layer facing the second channel layer 110 (Fig., 2B). Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Cheng & Gardner with the bonding structure further comprises: a third dielectric layer facing the first channel layer; and a fourth dielectric layer facing the second channel layer as taught by Bao in order to enhance protection from bonding processes and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art. Allowable Subject Matter Claims 1-15 are allowed over the prior art. Reasons for Allowance The following is an examiner’s statement of reasons for allowance: After further search and consideration, it is determined that the prior art neither anticipated nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination. The prior art does not teach or render not obvious “- - patterning the first semiconductor stack, the bonding structure, and the second semiconductor stack to form a fin structure- -” with combination of other claim limitations in claim 1. Also, the prior art does not teach or render not obvious “- - a bonding structure between the first semiconductor channel layer and second semiconductor channel layer- - etching back the first ILD layer and the first CESL layer to below the second semiconductor channel layer; forming second source/drain regions in contact with the second semiconductor channel layer and over the first ILD layer; depositing a second CSEL over the second source/drain regions and the first ILD layer; and depositing a second ILD layer on the second CESL. ” with combination of other claim limitations in claim 9. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Response to Arguments Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SU C KIM/Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Nov 17, 2023
Application Filed
Feb 10, 2026
Non-Final Rejection mailed — §103
May 10, 2026
Response Filed
Jul 21, 2026
Final Rejection mailed — §103
Sep 21, 2026
Response after Non-Final Action

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
78%
Grant Probability
66%
With Interview (-11.8%)
2y 9m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 923 resolved cases by this examiner. Grant probability derived from career allowance rate.

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