DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 7-13 are objected to because of the following informalities: claim 7, lines 3-4 contains the phrase, “separated to first and second portions,” which is grammatically incorrect. Claims 8-13 are objected to due to their dependency. Appropriate correction is required.
The examiner believes the above phrase should read separated into first and second portions.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (United States Patent Application Publication No. US 2020/0373331 A1, hereinafter “Kim”).
In reference to claim 1, Kim discloses a structure which meets the claim. Fig. 1A-1C, 19A-19D, 20, and 21 of Kim disclose a semiconductor device structure which comprises a first plurality of source/drain regions (130 over RX1) disposed along a first direction (X-direction), a second plurality of source/drain regions (130 over RX2) disposed along the first direction (X-direction) and spaced apart from the first plurality of source/drain regions (130 over RX1). A conductive feature (VC, 150) is disposed between the first (130 over RX1) and second (130 over RX2) pluralities of source/drain regions. A plurality of conductive contacts (CP1) are disposed over and in contact with the conductive feature (VC, 150). Each conductive contact (CP1) of the plurality of conductive contacts (CP1) is in contact with a source/drain region of the first plurality of source/drain regions (130 over RX1) and a source/drain region of the second plurality of source/drain regions (130 over RX2).
With regard to claim 2, a dielectric material (112b, 126) is disposed between the first (130 over RX1) and second (130 over RX2) pluralities of source/drain regions. The conductive feature (VC, 150) is disposed in the dielectric material (112b, 126).
In reference to claim 3, the dielectric material (112b, 126) completely surrounds the conductive feature (VC, 150). Thus the dielectric material (112b, 126) has a first height in a top view, and the conductive feature (VC, 150) has a second height substantially less than the first height in the top view.
With regard to claim 4, fig. 1A and 19A each shows a first gate electrode (GL – fig. 1A, GS – fig. 19A) disposed between adjacent source/drain regions of the first plurality of source/drain regions (130 over RX1). A second gate electrode (note unlabeled gate electrode along line X2-X2’ in fig. 1A and 19A) disposed between adjacent source/drain regions of the second plurality of source/drain regions (130 over RX2).
In reference to claim 5, the dielectric material (126) is disposed between the first (GL – fig. 1A, GS – fig. 19A) and second (note unlabeled gate electrode along line X2-X2’ in fig. 1A and 19A) gate electrodes.
With regard to claim 6, fig. 1A and 19A shows that the conductive feature (VC, 150) is disposed between the first (GL – fig. 1A, GS – fig. 19A) and second (note unlabeled gate electrode along line X2-X2’ in fig. 1A and 19A) gate electrodes.
Allowable Subject Matter
Claims 14-20 are allowed.
Claims 7-13 would be allowable if the text of claim 7 is corrected (see above section titled Claim Objections).
The following is a statement of reasons for the indication of allowable subject matter: in the examiner’s opinion, it would not be obvious to implement a semiconductor device structure which comprises first and second gate electrodes, a dielectric material such that the first gate electrode is separated into first and second portions by the dielectric material, and the second gate electrode is separated into third and fourth portions by the dielectric material, a first conductive feature disposed in the dielectric material and between the first and second portions of the first gate electrode and between the third and fourth portions of the second gate electrode, a first source/drain region disposed on a first side of the first portion of the first gate electrode, a second source/drain region disposed on a second side opposite the first side of the first portion of the first gate electrode, a third source/drain region disposed on a third side of the second portion of the first gate electrode, a fourth source/drain region disposed on a fourth side opposite the third side of the second portion of the first gate electrode, a first conductive contact disposed over and in electrical contact with the first conductive feature, the first source/drain region, and the third source/drain region; and a second conductive contact disposed over and in electrical contact with the first conductive feature, the second source/drain region, and the fourth source/drain region as described by the applicant in claim 7. In the examiner’s opinion, it would also not be obvious to implement a method for forming a semiconductor device structure which comprises forming a sacrificial gate electrode over a portion of a first stack of semiconductor layers and a portion of a second stack of semiconductor layers, recessing exposed portions of the first and second stacks of semiconductor layers not covered by the sacrificial gate electrode to expose first and second well portions on opposite sides of the portion of the first stack of semiconductor layers and to expose third and fourth well portions on opposite sides of the portion of the second stack of semiconductor layers, forming first, second, third, fourth source/drain regions on the respective first, second, third, fourth well portions, replacing the sacrificial gate electrode with a gate electrode, forming a dielectric material between the first and third source/drain regions such that the dielectric material separates the gate electrode into two portions, forming a first conductive contact over the first and third source/drain regions such that the first conductive contact is in contact with the dielectric material, forming a second conductive contact over the second and fourth source/drain regions such that the second conductive contact is in contact with the dielectric material, flipping over the semiconductor device structure; and forming a first conductive feature in the dielectric material that is electrically connected to the first and second conductive contacts as required by the applicant in claim 14.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30.
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/KEVIN QUINTO/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893