DETAILED ACTION
Election/Restriction
1. Applicant's election without traverse of Group I, claims 1-17, and newly added claims 21 - 23 is acknowledged.
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claim(s) 21, 23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by figs. 10 – 19 of Jung et al. (11211456).
With regard to claim 21, Jung et al. disclose a method (for example, see figs. 10 – 19), comprising:
forming a fin-shape structure (114, 124, fig. 12) protruding from a substrate (100, 105, fig. 12, functioning as a substrate);
forming a dummy gate stack (175, fig. 12) over a channel region (a semiconductor layer 124 functioning as a channel region) of the fin-shape structure (114, 124, fig. 12);
depositing a gate spacer layer (210, fig. 13) over the dummy gate stack (175, fig. 13);
recessing (recessing forming in an opening 190) a source/drain region (the region, forming in the opening 190, functioning as a source/drain region) of the fin-shape structure (114, 124) to form a source/drain trench (the opening 190, fig. 14);
forming a dielectric feature (220, fig. 14) on sidewalls of the source/drain trench (190, fig. 14);
depositing a first epitaxial layer (230, fig. 15) in the source/drain trench (190, fig. 15);
thinning (a third recess 205 may be formed on an outer sidewall of the inner spacer 220. Therefore, a thinning method forming on the outer sidewall of the inner spacer 220 for forming the third recess 205; for example, column 9, lines 19 - 21) a thickness of the dielectric feature (220);
depositing a second epitaxial layer (240, fig. 17) over the first epitaxial layer (230, fig. 17) in the source/drain trench (190),
the second epitaxial layer (240) having a dopant concentration greater than that of the first epitaxial layer (230; for example, see column 9, lines 57 – 58; and column 10, lines 5, 6);
after the depositing of the second epitaxial layer (240), replacing the dummy gate stack (175) with a metal gate structure (320, fig. 19).
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With regard to claim 23, Jung et al. disclose the first epitaxial layer (230) is spaced apart from the dielectric feature (220), and the second epitaxial layer (240) interfaces (interfaces at least a top or bottom corners) with the dielectric feature (220).
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 11, 12, 15 - 17 are rejected under 35 U.S.C. 103 as being unpatentable over Figs. 2, 10 – 19 of Jung et al. (11211456) in view of Chu et al. (2021/0376093).
With regard to claim 11, Jung et al. disclose a method (for example, see figs. 2, 10 – 19), comprising:
forming a fin-shape structure (114, 124, figs. 10, 12) including a stack atop a base (105), the stack comprising a plurality of channel layers (124; for example, see column 5, lines 14, 15) interleaved by a plurality of sacrificial layers (114, figs. 10, 12), the base (105) protruding from a substrate (100), the fin-shape structure (114, 124, figs. 10, 12) comprising a channel region (a channel region forming in the channel layer 124 and is directly under the a dummy gate stack 175) and a source/drain region (a source/drain region forming offset and on the side of a dummy gate stack 175);
forming a dummy gate stack (175, fig. 12) over the channel region of the fin-shape structure (114, 124);
depositing a gate spacer layer (210, fig. 13) over the dummy gate stack (175, fig. 13);
recessing the source/drain region to form a source/drain trench (a trench 190, for forming a source/drain feature, functioning as a source/drain trench) that exposes sidewalls of the channel layers (124, figs. 12, 14) and the sacrificial layers (114, figs. 12, 14);
selectively and partially recessing the sacrificial layers (114) to form a plurality of inner spacer recesses (recesses 200, fig. 13);
forming a plurality of inner spacers (220, fig. 13) in the inner spacer recesses;
depositing an epitaxial layer (230, fig. 15) in the source/drain trench (190);
selectively and partially recessing the inner spacers (220) to reduce a thickness of the inner spacers (220) (a recess 205 may be formed on an outer sidewall of the inner spacer 220. Therefore, the inner spacers 220 to reduce a thickness of the inner spacers 220; for example, column 9, lines 19 - 21);
depositing a doped epitaxial layer (240, fig. 17) over the epitaxial layer (230, fig. 17) in the source/drain trench (190), the doped epitaxial layer (240, fig. 17) being in contact with the channel layers (124);
after the depositing of the doped epitaxial layer (240, fig. 17), removing the dummy gate stack (240, figs. 17, 18);
releasing (forming an airgap 260 between the channel layers 124, fig. 18 in order to release the channel layers 124) the channel layers (124) in the channel region; and
forming a gate structure (330, fig. 2) wrapping around each of the channel layers (124).
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Chu et al. do not clearly disclose the epitaxial layer is an undoped epitaxial layer.
However, Chu et al. disclose the epitaxial layer is an undoped epitaxial layer. the epitaxial layer (244) is an undoped epitaxial layer (for example, see paragraph [0030], fig. 10A).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Jung et al.’s device to have the epitaxial layer is an undoped epitaxial layer as taught by Chu et al. in order to prevents too much dopants from diffusing into the channel members, as is known to one of ordinary skill in the art.
With regard to claim 12, Jung et al. disclose after the depositing of the doped epitaxial layer (240), a portion of the doped epitaxial layer (240) is vertically stacked between adjacent ones of the channel layers (124).
With regard to claim 15, Jung et al. disclose the depositing of the epitaxial layer (230, fig. 15) is performed after the selectively and partially recessing (recessing at recesses 205, fig. 14) of the inner spacers (220).
With regard to claim 16, Chu et al. disclose a portion (referred to as “244A” by examiner’s annotation shown in fig. 10A below) of the undoped epitaxial layer (244) is vertically stacked between a bottommost one of the channel layers (208) and a top surface of the base (a layer 203 functioning as the base).
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With regard to claim 17, Jung et al. disclose the gate structure (330), the channel layers (124), and the doped epitaxial layer (240) are portions of a p-type transistor (for example, see column 14, lines 63, 64).
6. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (11211456) in view of Chu et al. (2021/0376093) and further in view of Reznicek et al. (11315923).
With regard to claim 13, Jung et al. and Chu et al. do not clearly disclose the reduced thickness of the inner spacers is in a range between about 3 nm and about 6 nm.
However, Chu et al. disclose the reduced thickness (inner spacers 450 begins with a partial etch, so the thickness of the inner spacers 450 is reduced; for example, see column 8, lines 29, 30) of the inner spacers 450 is about 3 nm. (for example, see column 8, lines 49, 50).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Jung et al. and Chu et al.’s device to have the reduced thickness of the inner spacers is about 3 nm as taught by Chu et al. in order to minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
7. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over figs. 2, 10 – 19 of Jung et al. (11211456) in view of Chu et al. (2021/0376093) and further in view of figs. 49, 51 of Jung et al. (11211456).
With regard to claim 14, figs. 2, 10 – 19 of Jung et al. (11211456) do not clearly disclose the depositing of the epitaxial layer is performed prior to the selectively and partially recessing of the inner spacers.
However, figs. 49, 51 of Jung et al. (11211456) disclose the depositing of the epitaxial layer (850, fig. 49) is performed prior to the selectively and partially recessing of the inner spacers (520, fig. 51).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the figs. 2, 10 – 19 of Jung et al. (11211456) and Chu et al.’s device to have the depositing of the epitaxial layer is performed prior to the selectively and partially recessing of the inner spacers as taught by figs. 49, 51 of Jung et al. (11211456) in order to secure leakage currents may not be generated and minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
8. Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over figs. 10 – 19 of Jung et al. (11211456) in view of figs. 49, 51 of Jung et al. (11211456).
With regard to claim 22, figs. 10 – 19 of Jung et al. (11211456) do not clearly disclose the depositing of the first epitaxial layer is prior to the thinning of the thickness of the dielectric feature.
However, figs. 49, 51 of Jung et al. (11211456) disclose the depositing of the first epitaxial layer (830, fig. 49) is prior to the thinning (a recess 565 may be formed on an outer sidewall of the inner spacer 520. Therefore, a thinning method forming on the outer sidewall of the inner spacer 520 for forming the recess 565) of the thickness of the dielectric feature (520).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the figs. 10 – 19 of Jung et al. (11211456)’s device to have the depositing of the first epitaxial layer is prior to the thinning of the thickness of the dielectric feature as taught by figs. 49, 51 of Jung et al. (11211456) in order to secure leakage currents may not be generated and minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Allowable Subject Matter
9. Claims 1 - 10 are allowable over the prior art of record because none of these references disclose or can be combined to yield the claimed invention such as laterally recessing the second inner spacers to partially expose the second inner spacer recesses, wherein after the laterally recessing of the second inner spacers, the second inner spacers have a thickness less than the first inner spacers as recited in claim 1.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812
Prosecution Insights