DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Oath/Declaration
2. The oath/declaration filed on 12/17/2023 is acceptable.
Claim Rejections-35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
3. Claims 8-11 are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
In claim 8, step of “forming a plurality of spacer features on and a plurality of first recesses in the interconnect layer, adjacent two of the spacer features being spaced apart from each other by a corresponding one of the first recesses” is not clearly define the subject matter. For a purpose of examination, the examiner assumes that the above step should read as “forming a plurality of spacer features on and a plurality of first recesses on the interconnect layer, adjacent two of the spacer features being spaced apart from each other by a corresponding one of the first recesses”. Correction is required.
Claims 9-11 are depend on claim 8, then, they are also rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
4. Claims 1, 8, 12 and 18 are rejected under 35 U.S.C. 103(a) as being unpatentable over HUANG et al., hereafter “HUANG” (U.S. Publication No. 2023/0068760 A1) in view of TSAU et al., hereafter “TSAU” (U.S. Publication No. 2020/0152746 A1).
Regarding claim 1, HUANG discloses a method for manufacturing a semiconductor device, comprising:
forming a conductive structure (active region 11, see active region (22) in claim and Fig. 1 in Haase (U.S. Publication No. 2003/0211724 A1);
forming an interconnect layer (21) on the conductive structure (11), the interconnect layer (21) including a conductive interconnect (211) that is electrically connected to the conductive structure (11); and
forming a plurality of conductive features (40) and a plurality of spacer features (31) on the interconnect layer (21), adjacent two of the conductive features (40) being spaced apart from each other by a corresponding one of the spacer features (31), one of the conductive features (40) being electrically connected to the conductive interconnect (211), each of the spacer features including
a spacer layer (31) contacting lateral surfaces of two of the conductive features (40) that are adjacent to the spacer feature (31), and
a cover segment (90) disposed on the dielectric spacer layer (31), and cooperating with the dielectric spacer layer (31) to define an air gap (91, para [0061]) between said two of the conductive features (40) that are adjacent to the spacer feature (31) (Fig. 36).
HUANG discloses the features of the claimed invention as discussed above, but does not disclose a spacer id a dielectric spacer.
TSAU, however, discloses the spacer (150) includes insulating materials, such as silicon oxide, silicon nitride… (Fig. 1E and para [0028]). (Fig. 1G and para [0060]-0061]).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to use the spacer material teaching of TSAU with HUANG because such material substitution or replacement would have been considered a mere substitution of art-recognized equivalent values, i.e. to better support the conductive features. MPEP 2144.06.
Regarding claim 8, Dai discloses a method for manufacturing a semiconductor device, comprising:
forming an interconnect layer (21 that includes a conductive interconnect (211);
forming a plurality of spacer features (31) on and a plurality of first recesses (227, Fig. 6) on the interconnect layer (21), adjacent two of the spacer features (31) being spaced apart from each other by a corresponding one of the first recesses (227), one of the first recesses (227) exposing the conductive interconnect (211), each of the spacer features (31) including a spacer layer (31) having a caved shape, and forming a plurality of conductive features (40) in the first recesses (227, Fig. 7), and a cover segment (90, Fig. 36) disposed on the dielectric spacer layer (31), and cooperating with the dielectric spacer layer (31) to define an air gap (91, para [0061]) therebetween (Fig. 36).
(Figs. 1-2 and para [0014]-[0020]).
HUANG discloses the features of the claimed invention as discussed above, but does not disclose a spacer id a dielectric spacer.
TSAU, however, discloses the spacer (150) includes insulating materials, such as silicon oxide, silicon nitride… (Fig. 1E and para [0028]). (Fig. 1G and para [0060]-0061]).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to use the spacer material teaching of TSAU with HUANG because such material substitution or replacement would have been considered a mere substitution of art-recognized equivalent values, i.e. to better support the conductive features. MPEP 2144.06.
Regarding claim 12, Dai discloses a semiconductor device comprising:
a conductive structure (active region 11, see active region (22) in claim and Fig. 1 in Haase (U.S. Publication No. 2003/0211724 A1)
an interconnect layer (21) disposed on the conductive structure (11), and including a conductive interconnect (211) that is electrically connected to the conductive structure (11);
a first conductive feature (1st 40) and a second conductive feature (2nd 40), which are disposed on the interconnect layer (21), and one of which is electrically connected to the conductive interconnect (211); and
a spacer feature (31) disposed on the interconnect layer (21), configured to separate the first conductive feature (1st 40) and the second conductive feature (2nd 40) from each other, and including a spacer layer (31) contacting lateral surfaces of the first conductive feature (1st 40) and the second conductive feature (2nd 40), and a cover segment (90) disposed on the dielectric spacer layer (31), and cooperating with the dielectric spacer layer (31) to define an air gap (91) between said two of the conductive features (40) that are adjacent to the spacer feature (31) (Fig. 36).
HUANG discloses the features of the claimed invention as discussed above, but does not disclose a spacer id a dielectric spacer.
TSAU, however, discloses the spacer (150) includes insulating materials, such as silicon oxide, silicon nitride… (Fig. 1E and para [0028]). (Fig. 1G and para [0060]-0061]).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to use the spacer material teaching of TSAU with HUANG because such material substitution or replacement would have been considered a mere substitution of art-recognized equivalent values, i.e. to better support the conductive features. MPEP 2144.06.
Regarding claim 18, HAUNG and TSAU (citations to TSAU unless otherwise noted) discloses wherein the cover segment includes a dielectric spacer element (90) that contacts the dielectric spacer layer (31) (Fig. 36 in TSAU)..
5. Claims 1, 8, 12 and 18 are rejected under 35 U.S.C. 103(a) as being unpatentable over Dai et al., hereafter “Dai” (U.S. Publication No. 2021/0375751 A1) in view of Borsari et al., hereafter “Borsari” (U.S. Publication No. 2020/0373304 A1).
Regarding claim 1, Dai discloses a method for manufacturing a semiconductor device, comprising:
forming a conductive structure (102 or another suitable substrate, para [0022], see para [0038] in van der Straten et al. (U.S. Publication No. 2020/0118870 A1);
forming an interconnect layer (104) on the conductive structure (102), the interconnect layer (104) including a conductive interconnect (106) that is electrically connected to the conductive structure (102); and
forming a plurality of conductive features (112) and a plurality of spacer features (110) on the interconnect layer (104), adjacent two of the conductive features (112) being spaced apart from each other by a corresponding one of the spacer features (110), one of the conductive features (112) being electrically connected to the conductive interconnect (106), each of the spacer features including
a dielectric spacer layer (110, para [0023]) contacting lateral surfaces of two of the conductive features (112) that are adjacent to the spacer feature (110) (Figs. 1-2 and para [0014]-[0020]).
Dai discloses the features of the claimed invention as discussed above, but does not disclose a cover segment disposed on the dielectric spacer layer, and cooperating with the dielectric spacer layer to define an air gap between said two of the conductive features that are adjacent to the spacer feature.
Borsari, however, discloses a cover segment (132) disposed on the dielectric spacer layer (120/134/126), and cooperating with the dielectric spacer layer (120/126/134) to define an air gap (112) between said two of the conductive features (102/104) that are adjacent to the spacer feature (136) (Fig. 1G and para [0060]-0061]).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of Dai to form a cover segment disposed on the dielectric spacer layer, and cooperating with the dielectric spacer layer to define an air gap between said two of the conductive features that are adjacent to the spacer feature as taught by Borsari for a purpose of improving the rigidity of the conductive features and reducing manufacturing defects.
Regarding claim 8, Dai discloses a method for manufacturing a semiconductor device, comprising:
forming an interconnect layer (104) that includes a conductive interconnect (106);
forming a plurality of spacer features (110) on and a plurality of first recesses (gaps between 110, Fig. 6) in the interconnect layer (104), adjacent two of the spacer features (110) being spaced apart from each other by a corresponding one of the first recesses, one of the first recesses (gap between 110) exposing the conductive interconnect (106), each of the spacer features including a dielectric spacer layer (110, para [0023]) having a caved shape, and forming a plurality of conductive features(112) in the first recesses (Figs. 1-2 and para [0014]-[0020]).
Dai discloses the features of the claimed invention as discussed above, but does not disclose a cover segment disposed on the dielectric spacer layer, and cooperating with the dielectric spacer layer to define an air gap therebetween.
Borsari, however, discloses a cover segment (132) disposed on the dielectric spacer layer (120/134/126), and cooperating with the dielectric spacer layer (120/126/134) to define an air gap (112) therebetween (Fig. 1G and para [0060]-0061]).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of Dai to form a cover segment disposed on the dielectric spacer layer, and cooperating with the dielectric spacer layer to define an air gap as taught by Borsari for a purpose of improving the rigidity of the conductive features and reducing manufacturing defects.
Regarding claim 12, Dai discloses a semiconductor device comprising:
a conductive structure (102 or another suitable substrate, para [0022], see para [0038] in van der Straten et al. (U.S. Publication No. 2020/0118870 A1);
an interconnect layer (104) disposed on the conductive structure (102), and including a conductive interconnect (106) that is electrically connected to the conductive structure (102);
a first conductive feature (1st 112) and a second conductive feature (2nd 112), which are disposed on the interconnect layer (104), and one of which is electrically connected to the conductive interconnect (106); and
a spacer feature (110) disposed on the interconnect layer (104), configured to separate the first conductive feature (1st 112) and the second conductive feature (2nd 112) from each other, and including a dielectric spacer layer (110, para [0023]) contacting lateral surfaces of the first conductive feature (1st 112) and the second conductive feature (2nd 112) (Figs. 1-2 and para [0014]-[0020]).
Dai discloses the features of the claimed invention as discussed above, but does not disclose a cover segment disposed on the dielectric spacer layer, and cooperating with the dielectric spacer layer to define an air gap between said two of the conductive features that are adjacent to the spacer feature.
Borsari, however, discloses a cover segment (132) disposed on the dielectric spacer layer (120/134/126), and cooperating with the dielectric spacer layer (120/126/134) to define an air gap (112) between said the first conductive feature (1st 102/1st 104) and the second the conductive features (2nd 102/2nd 104) that are adjacent to the spacer feature (136) (Fig. 1G and para [0060]-0061]).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of Dai to form a cover segment disposed on the dielectric spacer layer, and cooperating with the dielectric spacer layer to define an air gap between the first conductive feature and the second conductive feature that are adjacent to the spacer feature as taught by Borsari for a purpose of improving the rigidity of the conductive features and reducing manufacturing defects.
Regarding claim 18, Dai and Borsari (citations to Dai unless otherwise noted) discloses wherein the cover segment includes a dielectric spacer element (132) that contacts the dielectric spacer layer (136) (Fig. 1G in Brsari).
Allowable Subject Matter
6. The following is a statement of reason for the indication of allowable subject matter:
Claims 2-7, 9-11, 13-17 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Phuc T. Dang whose telephone number is 571-272-1776. The examiner can normally be reached on 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHUC T DANG/Primary Examiner, Art Unit 2897