DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation "the base region" in line 9 . There is insufficient antecedent basis for this limitation in the claim because prior to the claimed limitation of "the base region" there is no claimed limitation of " a base region" . Applicant is directed to look at line 4 introducing “an intrinsic base” and line 5 “the intrinsic base region”, then line 6 “the intrinsic base”. It is recommended to introduce one limitation and keep the same phrase throughout the claim(s). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 4-5, 13-14, 16, 18, 20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Camillo-Castillo et al. (US 2015/0060950 A1 hereinafter referred to as “Camillo-Castillo”) . With respect to claim 1 , Camillo-Castillo discloses, in Figs.1-8, A structure comprising: a sub-collector region (20) ; a collector region (18) above the sub-collector region (20) (see Par.[0017] wherein a collector 18 is disposed in the active device region 14 and a subcollector 20 is disposed in the substrate 10 beneath the collector 18 ; t he collector 18 and subcollector 20 may comprise an electrically-active dopant, such as an n-type impurity species from Group V of the Periodic Table (e.g., phosphorus (P), arsenic (As), or antimony (Sb)) that is effective to impart n-type conductivity in silicon ) ; an intrinsic base (22 /24 ) above the collector region (18) (see Par.[0018]-[00 23 ] wherein a n intrinsic base layer 22 is formed as a continuous additive layer on the top surface 10a of the substrate 10 in active device region 14 ; t he intrinsic base layer 22 is coupled with the collector 18 and may directly contact the collector 18 ; t he intrinsic base layer 22 may be comprised of a semiconductor material, such as silicon-germanium (SiGe) including silicon (Si) and germanium (Ge) in an alloy with the silicon content ranging from 95 atomic percent to 50 atomic percent and the germanium content ranging from 5 atomic percent to 50 atomic percent ; t he germanium content of the intrinsic base layer 22 may be uniform or the germanium content of intrinsic base layer 22 may be graded and/or stepped across the thickness of intrinsic base layer 22 ; t he single-crystal semiconductor material of the active device region 14 serves as a crystalline template for the growth of the single crystal section 24 of intrinsic base layer 22 that is coextensive with the active device region 14 ) ; an emitter (28) above the intrinsic base region (22) (see Par.[0048]-[0051] wherein the emitter 68 may be comprised of polysilicon or polycrystalline silicon-germanium deposited by CVD or LPCVD and heavily doped with a concentration of a dopant, such as an impurities species from Group V of the Periodic Table, such as phosphorus (P), arsenic (As), to impart n-type conductivity ) ; and an extrinsic base (62) on the intrinsic base (22) and adjacent to the emitter (68) , wherein the collector region (22) includes an undercut profile comprising lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extend to a narrow section between the sub-collector region (22) and the base region (62) ( see Par.[0044]-[0045] wherein a n extrinsic base layer 62 is formed on the top surface 22a of the intrinsic base layer 22 ; the extrinsic base layer 62 may be comprised of polycrystalline semiconductor material (e.g., polysilicon or polycrystalline SiGe) ; see Fig.4B, Par.[0035] wherein t he sidewalls 40, 42 in the lateral extensions 44, 45 may be characterized as non-rectangular polygons, such as triangular-shaped (FIG. 4B) or diamond-shaped (FIG. 4C) ) . With respect to claim 4 , Camillo-Castillo discloses, in Figs.1-8, the structure, wherein the undercut profile comprises lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extending to a narrow section between the sub-collector region and the extrinsic base (see Par.[0044]-[0045] wherein an extrinsic base layer 62 is formed on the top surface 22a of the intrinsic base layer 22; the extrinsic base layer 62 may be comprised of polycrystalline semiconductor material (e.g., polysilicon or polycrystalline SiGe); see Fig.4B, Par.[0035] wherein the sidewalls 40, 42 in the lateral extensions 44, 45 may be characterized as non-rectangular polygons, such as triangular-shaped (FIG. 4B) or diamond-shaped (FIG. 4C)). With respect to claim 5 , Camillo-Castillo discloses, in Figs.1-8, the structure, wherein the narrow section comprises a straight sidewall profile (see Par.[0044]-[0045] wherein an extrinsic base layer 62 is formed on the top surface 22a of the intrinsic base layer 22; the extrinsic base layer 62 may be comprised of polycrystalline semiconductor material (e.g., polysilicon or polycrystalline SiGe); see Fig.4B, Par.[0035] wherein the sidewalls 40, 42 in the lateral extensions 44, 45 may be characterized as non-rectangular polygons, such as triangular-shaped (FIG. 4B) or diamond-shaped (FIG. 4C)). With respect to claim 13 , Camillo-Castillo discloses, in Figs.1-8, t he structure, further comprising an airgap (44) extending to the upper and lower inwardly tapered sidewalls, and further surrounding the undercut profile (see Par.[0036]-[0037] wherein air gaps 58, 59 are formed in the lateral extensions 44, 45 between the sloped sidewalls 40, 42 and the bottom side of the intrinsic base layer 22 ) . With respect to claim 14 , Camillo-Castillo discloses, in Figs.1-8, a structure comprising: a sub-collector region (20) comprising a first semiconductor material; an intrinsic base (22) ; an emitter (68) ; an extrinsic base (62) on the intrinsic base (22) and adjacent to the emitter (68) ; and a collector (18) comprising an undercut profile comprising lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extending to a narrow section between the sub-collector region and the intrinsic base (see Par.[0017] wherein a collector 18 is disposed in the active device region 14 and a subcollector 20 is disposed in the substrate 10 beneath the collector 18; the collector 18 and subcollector 20 may comprise an electrically-active dopant, such as an n-type impurity species from Group V of the Periodic Table (e.g., phosphorus (P), arsenic (As), or antimony (Sb)) that is effective to impart n-type conductivity in silicon ; see Par.[0018]-[0023] wherein an intrinsic base layer 22 is formed as a continuous additive layer on the top surface 10a of the substrate 10 in active device region 14; the intrinsic base layer 22 is coupled with the collector 18 and may directly contact the collector 18; the intrinsic base layer 22 may be comprised of a semiconductor material, such as silicon-germanium (SiGe) including silicon (Si) and germanium (Ge) in an alloy with the silicon content ranging from 95 atomic percent to 50 atomic percent and the germanium content ranging from 5 atomic percent to 50 atomic percent; the germanium content of the intrinsic base layer 22 may be uniform or the germanium content of intrinsic base layer 22 may be graded and/or stepped across the thickness of intrinsic base layer 22; the single-crystal semiconductor material of the active device region 14 serves as a crystalline template for the growth of the single crystal section 24 of intrinsic base layer 22 that is coextensive with the active device region 14 ; see Par.[0048]-[0051] wherein the emitter 68 may be comprised of polysilicon or polycrystalline silicon-germanium deposited by CVD or LPCVD and heavily doped with a concentration of a dopant, such as an impurities species from Group V of the Periodic Table, such as phosphorus (P), arsenic (As), to impart n-type conductivity ; see Par.[0044]-[0045] wherein an extrinsic base layer 62 is formed on the top surface 22a of the intrinsic base layer 22; the extrinsic base layer 62 may be comprised of polycrystalline semiconductor material (e.g., polysilicon or polycrystalline SiGe); see Fig.4B, Par.[0035] wherein the sidewalls 40, 42 in the lateral extensions 44, 45 may be characterized as non-rectangular polygons, such as triangular-shaped (FIG. 4B) or diamond-shaped (FIG. 4C)). With respect to claim 16 , Camillo-Castillo discloses, in Figs.1-8, t he structure, wherein the narrow section comprises a straight sidewall profile (see Par.[0044]-[0045] wherein an extrinsic base layer 62 is formed on the top surface 22a of the intrinsic base layer 22; the extrinsic base layer 62 may be comprised of polycrystalline semiconductor material (e.g., polysilicon or polycrystalline SiGe); see Fig.4B, Par.[0035] wherein the sidewalls 40, 42 in the lateral extensions 44, 45 may be characterized as non-rectangular polygons, such as triangular-shaped (FIG. 4B) or diamond-shaped (FIG. 4C)). With respect to claim 18 , Camillo-Castillo discloses, in Figs.1-8, t he structure, further comprising an airgap surrounding the undercut profile (see Par.[0036]-[0037] wherein air gaps 58, 59 are formed in the lateral extensions 44, 45 between the sloped sidewalls 40, 42 and the bottom side of the intrinsic base layer 22) . With respect to claim 20 , Camillo-Castillo discloses, in Figs.1-8, a method comprising: forming a sub-collector region (20) ; forming a collector (18) above the sub-collector region (20) ; forming an intrinsic base ( 22 ) above the collector region (18) ; forming an emitter (68) above the intrinsic base region (22) ; forming an extrinsic base (62) on the intrinsic base (22) and adjacent to the emitter (68) ; and forming an undercut in the collector region (18) , the undercut comprising lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extending to a narrow section between the sub-collector region and the extrinsic base (see Par.[0017] wherein a collector 18 is disposed in the active device region 14 and a subcollector 20 is disposed in the substrate 10 beneath the collector 18; the collector 18 and subcollector 20 may comprise an electrically-active dopant, such as an n-type impurity species from Group V of the Periodic Table (e.g., phosphorus (P), arsenic (As), or antimony (Sb)) that is effective to impart n-type conductivity in silicon; see Par.[0018]-[0023] wherein an intrinsic base layer 22 is formed as a continuous additive layer on the top surface 10a of the substrate 10 in active device region 14; the intrinsic base layer 22 is coupled with the collector 18 and may directly contact the collector 18; the intrinsic base layer 22 may be comprised of a semiconductor material, such as silicon-germanium (SiGe) including silicon (Si) and germanium (Ge) in an alloy with the silicon content ranging from 95 atomic percent to 50 atomic percent and the germanium content ranging from 5 atomic percent to 50 atomic percent; the germanium content of the intrinsic base layer 22 may be uniform or the germanium content of intrinsic base layer 22 may be graded and/or stepped across the thickness of intrinsic base layer 22; the single-crystal semiconductor material of the active device region 14 serves as a crystalline template for the growth of the single crystal section 24 of intrinsic base layer 22 that is coextensive with the active device region 14; see Par.[0048]-[0051] wherein the emitter 68 may be comprised of polysilicon or polycrystalline silicon-germanium deposited by CVD or LPCVD and heavily doped with a concentration of a dopant, such as an impurities species from Group V of the Periodic Table, such as phosphorus (P), arsenic (As), to impart n-type conductivity; see Par.[0044]-[0045] wherein an extrinsic base layer 62 is formed on the top surface 22a of the intrinsic base layer 22; the extrinsic base layer 62 may be comprised of polycrystalline semiconductor material (e.g., polysilicon or polycrystalline SiGe); see Fig.4B, Par.[0035] wherein the sidewalls 40, 42 in the lateral extensions 44, 45 may be characterized as non-rectangular polygons, such as triangular-shaped (FIG. 4B) or diamond-shaped (FIG. 4C)) . Claims 1-2, 4-6, 14, 16, 20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Yoon et al. (US 2003/0077870 A1 hereinafter referred to as “Yoon”) . With respect to claim 1 , Yoon discloses, in Figs.1-7, a structure comprising: a sub-collector region (102) ; a collector region (104, 106, 108) above the sub-collector region (102) ; an intrinsic base (110) above the collector region (104, 106, 108) ; an emitter (112, 116) above the intrinsic base region (110) (see Par.[0015]-[0016] wherein an etch stop InP layer 104 is inserted between a first sub-collector InGaAs layer 102 and a second sub-collector InGaAs layer 106; a second sub-collector InGaAs layers 102, 106/a base InGaAs layer 110/an emitter InGaAs layer 116 and an etch stop InP layer 104/a collector InP layer 108/a first and a second emitter InP layers 112,114) ; and an extrinsic base (122a) on the intrinsic base (110) and adjacent to the emitter (112, 114) , wherein the collector region (104, 106, 108) includes an undercut profile comprising lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extend to a narrow section between the sub-collector region (102) and the base region (110) (see Par.[0026] wherein a base metal layer(122a) and a collector metal layer 122b are formed as described in FIG. 7 ; see Fig.7 wherein an undercut profile comprising lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extend to a narrow section between the sub-collector region and the intrinsic base region ) . With respect to claim 2 , Yoon discloses, in Figs.1-7, t he structure, wherein the sub-collector region (102) and the intrinsic base (110) comprise a semiconductor material which is different than a semiconductor material of the collector (104, 106, 108) (see Par.[0015]-[0016] wherein an etch stop InP layer 104 is inserted between a first sub-collector InGaAs layer 102 and a second sub-collector InGaAs layer 106; a second sub-collector InGaAs layers 102, 106/a base InGaAs layer 110/an emitter InGaAs layer 116 and an etch stop InP layer 104/a collector InP layer 108/a first and a second emitter InP layers 112,114). With respect to claim 4 , Yoon discloses, in Figs.1-7, t he structure, wherein the undercut profile comprises lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extending to a narrow section between the sub-collector region and the extrinsic base ( see Fig.7 wherein an undercut profile comprising lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extend to a narrow section between the sub-collector region and the intrinsic base region). With respect to claim 5 , Yoon discloses, in Figs.1-7, t he structure, wherein the narrow section comprises a straight sidewall profile (see Fig.7 wherein an undercut profile comprising lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extend to a narrow section between the sub-collector region and the intrinsic base region). With respect to claim 6 , Yoon discloses, in Figs.1-7, t he structure, further comprising a layer (106) of semiconductor material extending through the narrow region of the collector (104, 106, 108) , which is different than a semiconductor material of the collector region (104, 108) (see Par.[0015]-[0016] wherein an etch stop InP layer 104 is inserted between a first sub-collector InGaAs layer 102 and a second sub-collector InGaAs layer 106; a second sub-collector InGaAs layers 102, 106/a base InGaAs layer 110/an emitter InGaAs layer 116 and an etch stop InP layer 104/a collector InP layer 108/a first and a second emitter InP layers 112,114). With respect to claim 14 , Yoon discloses, in Figs.1-7, a structure comprising: a sub-collector region (102) comprising a first semiconductor material; an intrinsic base (110) ; an emitter (112, 114) ; an extrinsic base (122a) on the intrinsic base (110) and adjacent to the emitter (112, 114) ; and a collector (104, 106, 10) comprising an undercut profile comprising lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extending to a narrow section between the sub-collector region and the intrinsic base (see Par.[0015]-[0016] wherein an etch stop InP layer 104 is inserted between a first sub-collector InGaAs layer 102 and a second sub-collector InGaAs layer 106; a second sub-collector InGaAs layers 102, 106/a base InGaAs layer 110/an emitter InGaAs layer 116 and an etch stop InP layer 104/a collector InP layer 108/a first and a second emitter InP layers 112,114 ; see Par.[0026] wherein a base metal layer(122a) and a collector metal layer 122b are formed as described in FIG. 7; see Fig.7 wherein an undercut profile comprising lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extend to a narrow section between the sub-collector region and the intrinsic base region) . With respect to claim 16 , Yoon discloses, in Figs.1-7, t he structure, wherein the narrow section comprises a straight sidewall profile (see Fig.7 wherein an undercut profile comprising lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extend to a narrow section between the sub-collector region and the intrinsic base region). With respect to claim 20 , Yoon discloses, in Figs.1-7, a method comprising: forming a sub-collector region (102) ; forming a collector (104, 106, 108) above the sub-collector region (102) ; forming an intrinsic base (100) above the collector region (104, 106, 108) ; forming an emitter (112, 114) above the intrinsic base region ( 110 ) ; forming an extrinsic base (122a) on the intrinsic base (110) and adjacent to the emitter (112, 114) ; and forming an undercut in the collector region (104, 106, 108) , the undercut comprising lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extending to a narrow section between the sub-collector region and the extrinsic base (see Par.[0015]-[0016] wherein an etch stop InP layer 104 is inserted between a first sub-collector InGaAs layer 102 and a second sub-collector InGaAs layer 106; a second sub-collector InGaAs layers 102, 106/a base InGaAs layer 110/an emitter InGaAs layer 116 and an etch stop InP layer 104/a collector InP layer 108/a first and a second emitter InP layers 112,114; see Par.[0026] wherein a base metal layer(122a) and a collector metal layer 122b are formed as described in FIG. 7; see Fig.7 wherein an undercut profile comprising lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extend to a narrow section between the sub-collector region and the intrinsic base region) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 1-5, 14-15, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Donkers et al. (US 2023/0215937 A1 hereinafter referred to as “Donkers”) in view of Camillo-Castillo (US 2015/0060950 ) . With respect to claim 1 , Donkers discloses, in Figs.1-24, a structure comprising: a sub-collector region (102) ; a collector region (104) above the sub-collector region (102) ; an intrinsic base (113) above the collector region (104) ; an emitter (116) above the intrinsic base region (113) ; and an extrinsic base (114) on the intrinsic base (113) and adjacent to the emitter (116) wherein the collector region (104) includes an undercut profile comprising lower inwardly tapered sidewalls and upper inwardly tapered sidewalls (see Fig.6, Par.[0033]-[0035] wherein the buried n-layer collector 102 is positioned over the n-epi collector layer 104 ; base regions 113, 114, adjacent to emitter regions 116 ; see Fig.6 wherein inside sidewalls of collector 104 a re tapered ). However, Donkers does not exclusively disclose that the collector region includes an undercut profile comprising lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extend to a narrow section between the sub-collector region and the base region . Camillo-Castillo discloses, in Figs.1-8, A structure comprising: a sub-collector region (20); a collector region (18) above the sub-collector region (20) (see Par.[0017] wherein a collector 18 is disposed in the active device region 14 and a subcollector 20 is disposed in the substrate 10 beneath the collector 18; the collector 18 and subcollector 20 may comprise an electrically-active dopant, such as an n-type impurity species from Group V of the Periodic Table (e.g., phosphorus (P), arsenic (As), or antimony (Sb)) that is effective to impart n-type conductivity in silicon); an intrinsic base (22/24) above the collector region (18) (see Par.[0018]-[0023] wherein an intrinsic base layer 22 is formed as a continuous additive layer on the top surface 10a of the substrate 10 in active device region 14; the intrinsic base layer 22 is coupled with the collector 18 and may directly contact the collector 18; the intrinsic base layer 22 may be comprised of a semiconductor material, such as silicon-germanium (SiGe) including silicon (Si) and germanium (Ge) in an alloy with the silicon content ranging from 95 atomic percent to 50 atomic percent and the germanium content ranging from 5 atomic percent to 50 atomic percent. The germanium content of the intrinsic base layer 22 may be uniform or the germanium content of intrinsic base layer 22 may be graded and/or stepped across the thickness of intrinsic base layer 22; the single-crystal semiconductor material of the active device region 14 serves as a crystalline template for the growth of the single crystal section 24 of intrinsic base layer 22 that is coextensive with the active device region 14); an emitter (28) above the intrinsic base region (22) (see Par.[0048]-[0051] wherein the emitter 68 may be comprised of polysilicon or polycrystalline silicon-germanium deposited by CVD or LPCVD and heavily doped with a concentration of a dopant, such as an impurities species from Group V of the Periodic Table, such as phosphorus (P), arsenic (As), to impart n-type conductivity); and an extrinsic base (62) on the intrinsic base (22) and adjacent to the emitter (68), wherein the collector region (22) includes an undercut profile comprising lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extend to a narrow section between the sub-collector region (22) and the base region (62) (see Par.[0044]-[0045] wherein an extrinsic base layer 62 is formed on the top surface 22a of the intrinsic base layer 22; the extrinsic base layer 62 may be comprised of polycrystalline semiconductor material (e.g., polysilicon or polycrystalline SiGe); see Fig.4B, Par.[0035] wherein the sidewalls 40, 42 in the lateral extensions 44, 45 may be characterized as non-rectangular polygons, such as triangular-shaped (FIG. 4B) or diamond-shaped (FIG. 4C)). Donkers and Camillo-Castillo are analogous art because they are all directed to a HBT device , and one of ordinary skill in the art would have had a reasonable expectation of s uccess by modify ing Donkers to include Camillo-Castillo because they are from the same field of endeavor. Therefore, i t would have been obvious to one of ordinary skill in the art at the time t he invention was made to modify the profile shape of collector of HBT in Donkers by including collector shape characterized as non-rectangular polygons, such as triangular-shaped or diamond-shaped as t aught by Camillo-Castillo in order to utilize the collector layer sidewalls laterally shape , so as the collector electrode may be more close to the base and the emitter, thereby the resistance may be reduced further for enhanced transistor performance . With respect to claim 2 , Donkers discloses, in Figs.1-24, t he structure, wherein the sub-collector region (102) and the intrinsic base (113) comprise a semiconductor material which is different than a semiconductor material of the collector (104) (see Par.[0027] wherein a semiconductor structure 3 including a buried n-type collector layer 102 and an n-type epitaxial collector layer 104 formed over a p-type wafer substrate layer 101 and separated from one another by a barrier diffusion layer 103 ; a s will be appreciated, the p-type wafer substrate layer 101 may be implemented as a bulk silicon substrate, monocrystalline silicon (doped or undoped), or any semiconductor material including, as non-limiting examples, Si, SiC, SiGe, SiGeC, Ge, GaAs, InAs, InP as well as other Group III-V compound semiconductors or any combination thereof ; see Par.[0036] wherein the epi and poly base stacks 113A, 113B is controlled to form the p-type epitaxial Si/SiGe:C/Si base stack 113A with a SiGe:C layer having an atomic percentage of 10-35% germanium and a p-type doping concentration in the range of 1×10.sup.19-1×10.sup.21 cm.sup.−3. In addition, the epitaxial stack portion 113A may include stacked or sandwiched epi-Si layers positioned above and below the epitaxial SiGe:C layer which have lower p-type doping concentrations (e.g., in the range of 1×10.sup.17-1×10.sup.19 cm.sup.−3) ) . With respect to claim 3 , Donkers discloses, in Figs.1-24, t he structure, wherein the semiconductor material of the sub-collector (102) comprises at least n-type SiGe, the intrinsic base (113) comprises p-type SiGe and the collector (104) comprises n-type Si (see Par.[0027] wherein a semiconductor structure 3 including a buried n-type collector layer 102 and an n-type epitaxial collector layer 104 formed over a p-type wafer substrate layer 101 and separated from one another by a barrier diffusion layer 103; as will be appreciated, the p-type wafer substrate layer 101 may be implemented as a bulk silicon substrate, monocrystalline silicon (doped or undoped), or any semiconductor material including, as non-limiting examples, Si, SiC, SiGe, SiGeC, Ge, GaAs, InAs, InP as well as other Group III-V compound semiconductors or any combination thereof; see Par.[0036] wherein the epi and poly base stacks 113A, 113B is controlled to form the p-type epitaxial Si/SiGe:C/Si base stack 113A with a SiGe:C layer having an atomic percentage of 10-35% germanium and a p-type doping concentration in the range of 1×10.sup.19-1×10.sup.21 cm.sup.−3. In addition, the epitaxial stack portion 113A may include stacked or sandwiched epi-Si layers positioned above and below the epitaxial SiGe:C layer which have lower p-type doping concentrations (e.g., in the range of 1×10.sup.17-1×10.sup.19 cm.sup.−3)). With respect to claim 4 , Camillo-Castillo discloses, in Figs.1-8, t he structure, wherein the undercut profile comprises lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extending to a narrow section between the sub-collector region and the extrinsic base (see Par.[0044]-[0045] wherein an extrinsic base layer 62 is formed on the top surface 22a of the intrinsic base layer 22; the extrinsic base layer 62 may be comprised of polycrystalline semiconductor material (e.g., polysilicon or polycrystalline SiGe); see Fig.4B, Par.[0035] wherein the sidewalls 40, 42 in the lateral extensions 44, 45 may be characterized as non-rectangular polygons, such as triangular-shaped (FIG. 4B) or diamond-shaped (FIG. 4C)). With respect to claim 5 , Camillo-Castillo discloses, in Figs.1-8, t he structure, wherein the narrow section comprises a straight sidewall profile (see Par.[0044]-[0045] wherein an extrinsic base layer 62 is formed on the top surface 22a of the intrinsic base layer 22; the extrinsic base layer 62 may be comprised of polycrystalline semiconductor material (e.g., polysilicon or polycrystalline SiGe); see Fig.4B, Par.[0035] wherein the sidewalls 40, 42 in the lateral extensions 44, 45 may be characterized as non-rectangular polygons, such as triangular-shaped (FIG. 4B) or diamond-shaped (FIG. 4C)). With respect to claim 14 , Donkers discloses, in Figs.1-24, a structure comprising: a sub-collector region (102) comprising a first semiconductor material; an intrinsic base (113) ; an emitter (116) ; an extrinsic base (114) on the intrinsic base and adjacent to the emitter (113) ; and a collector (104) comprising an undercut profile comprising lower inwardly tapered sidewalls and upper inwardly tapered sidewalls (see Fig.6, Par.[0033]-[0035] wherein the buried n-layer collector 102 is positioned over the n-epi collector layer 104; base regions 113, 114, adjacent to emitter regions 116; see Fig.6 wherein inside sidewalls of collector 104 are tapered). However, Donkers does not exclusively disclose that the collector region includes an undercut profile comprising lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extend to a narrow section between the sub-collector region and the base region. Camillo-Castillo discloses, in Figs.1-8, a structure comprising: a sub-collector region (20) comprising a first semiconductor material; an intrinsic base (22); an emitter (68); an extrinsic base (62) on the intrinsic base (22) and adjacent to the emitter (68); and a collector (18) comprising an undercut profile comprising lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extending to a narrow section between the sub-collector region and the intrinsic base (see Par.[0017] wherein a collector 18 is disposed in the active device region 14 and a subcollector 20 is disposed in the substrate 10 beneath the collector 18; the collector 18 and subcollector 20 may comprise an electrically-active dopant, such as an n-type impurity species from Group V of the Periodic Table (e.g., phosphorus (P), arsenic (As), or antimony (Sb)) that is effective to impart n-type conductivity in silicon; see Par.[0018]-[0023] wherein an intrinsic base layer 22 is formed as a continuous additive layer on the top surface 10a of the substrate 10 in active device region 14; the intrinsic base layer 22 is coupled with the collector 18 and may directly contact the collector 18; the intrinsic base layer 22 may be comprised of a semiconductor material, such as silicon-germanium (SiGe) including silicon (Si) and germanium (Ge) in an alloy with the silicon content ranging from 95 atomic percent to 50 atomic percent and the germanium content ranging from 5 atomic percent to 50 atomic percent; the germanium content of the intrinsic base layer 22 may be uniform or the germanium content of intrinsic base layer 22 may be graded and/or stepped across the thickness of intrinsic base layer 22; the single-crystal semiconductor material of the active device region 14 serves as a crystalline template for the growth of the single crystal section 24 of intrinsic base layer 22 that is coextensive with the active device region 14; see Par.[0048]-[0051] wherein the emitter 68 may be comprised of polysilicon or polycrystalline silicon-germanium deposited by CVD or LPCVD and heavily doped with a concentration of a dopant, such as an impurities species from Group V of the Periodic Table, such as phosphorus (P), arsenic (As), to impart n-type conductivity; see Par.[0044]-[0045] wherein an extrinsic base layer 62 is formed on the top surface 22a of the intrinsic base layer 22; the extrinsic base layer 62 may be comprised of polycrystalline semiconductor material (e.g., polysilicon or polycrystalline SiGe); see Fig.4B, Par.[0035] wherein the sidewalls 40, 42 in the lateral extensions 44, 45 may be characterized as non-rectangular polygons, such as triangular-shaped (FIG. 4B) or diamond-shaped (FIG. 4C)). Donkers and Camillo-Castillo are analogous art because they are all directed to a HBT device, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Donkers to include Camillo-Castillo because they are from the same field of endeavor. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the profile shape of collector of HBT in Donkers by including collector shape characterized as non-rectangular polygons, such as triangular-shaped or diamond-shaped as taught by Camillo-Castillo in order to utilize the collector layer sidewalls laterally shape, so as the collector electrode may be more close to the base and the emitter, thereby the resistance may be reduced further for enhanced transistor performance. With respect to claim 15 , Donkers discloses, in Figs.1-24, t he structure, wherein the first semiconductor material comprises SiGe, the intrinsic base comprise p-type doped SiGe and the sub-collector region comprises n-type doped SiGe and the semiconductor material of the collector comprises Si (see Par.[0027] wherein a semiconductor structure 3 including a buried n-type collector layer 102 and an n-type epitaxial collector layer 104 formed over a p-type wafer substrate layer 101 and separated from one another by a barrier diffusion layer 103; as will be appreciated, the p-type wafer substrate layer 101 may be implemented as a bulk silicon substrate, monocrystalline silicon (doped or undoped), or any semiconductor material including, as non-limiting examples, Si, SiC, SiGe, SiGeC, Ge, GaAs, InAs, InP as well as other Group III-V compound semiconductors or any combination thereof; see Par.[0036] wherein the epi and poly base stacks 113A, 113B is controlled to form the p-type epitaxial Si/SiGe:C/Si base stack 113A with a SiGe:C layer having an atomic percentage of 10-35% germanium and a p-type doping concentration in the range of 1×10.sup.19-1×10.sup.21 cm.sup.−3. In addition, the epitaxial stack portion 113A may include stacked or sandwiched epi-Si layers positioned above and below the epitaxial SiGe:C layer which have lower p-type doping concentrations (e.g., in the range of 1×10.sup.17-1×10.sup.19 cm.sup.−3)). With respect to claim 19 , Donkers discloses, in Figs.1-24, t he structure, wherein the sub-collector region comprising both Si material and SiGe material, with the SiGe material being an etch stop layer (see Par.[0027] wherein a semiconductor structure 3 including a buried n-type collector layer 102 and an n-type epitaxial collector layer 104 formed over a p-type wafer substrate layer 101 and separated from one another by a barrier diffusion layer 103; as will be appreciated, the p-type wafer substrate layer 101 may be implemented as a bulk silicon substrate, monocrystalline silicon (doped or undoped), or any semiconductor material including, as non-limiting examples, Si, SiC, SiGe, SiGeC, Ge, GaAs, InAs, InP as well as other Group III-V compound semiconductors or any combination thereof; see Par.[0036] wherein the epi and poly base stacks 113A, 113B is controlled to form the p-type epitaxial Si/SiGe:C/Si base stack 113A with a SiGe:C layer having an atomic percentage of 10-35% germanium and a p-type doping concentration in the range of 1×10.sup.19-1×10.sup.21 cm.sup.−3. In addition, the epitaxial stack portion 113A may include stacked or sandwiched epi-Si layers positioned above and below the epitaxial SiGe:C layer which have lower p-type doping concentrations (e.g., in the range of 1×10.sup.17-1×10.sup.19 cm.sup.−3)). Allowable Subject Matter Claims 7, 10, 17 are objected to as being dependent upon a rejected base claims 1, 14, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 8-9, 11-12 are also objected for being dependent to the objected base claims 1, 14 respectively. Citation of Pertinent Prior Art The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure. 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