DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Claims 1-8 in the reply filed on 03/19/2026 is acknowledged.
Newly submitted claims 21-32 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: Claims 21-26 are for a method of forming a semiconductor device structure that is mutually exclusive from the elected Group I. Claims 27-32 are for a method of forming a semiconductor device structure that is mutually exclusive from the Claims 21-26 and also mutually exclusive from the elected Group I.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 21-32 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/17/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6 and 8 are rejected under 35 U.S.C. 102 as being anticipated by Tsai et al. (US 12,538,533 B2; hereinafter Tsai )
Regarding claim 1, Tsai teaches a method for forming a semiconductor device structure, comprising: forming nanostructures ( Fig. 1G: nanostructures 106 ) over a substrate ( Fig. 1G: substrate 102 ); forming a gate structure wrapped around the nanostructures ( Col. 6 lines 31 - 34 The dummy gate dielectric layer 126 and the dummy gate electrode layer 128 may be replaced by the following steps to form a real gate structure with a high-k dielectric layer and a metal gate electrode layer ); forming source/drain epitaxial structures ( Col. 8 lines 21 - 23a source/drain epitaxial structure 138 is formed in the source/drain opening, as shown in FIG. 1L ) over opposite sides of the nanostructures ( Fig. 1L #138 is formed over #106 ); forming an interlayer dielectric structure ( Fig. 1M: inter-layer dielectric structure 140 ) over the source/drain epitaxial structures ( Fig. 1M #138 ); etching the interlayer dielectric structure ( Col. 9 lines 25 – 27 Afterwards, a planarizing process or an etch-back process may be performed on the ILD structure 140 until the top surface of the dummy gate structure 124 is exposed ) to form an opening exposing the source/drain epitaxial structures ( Col. 6 lines 26 – 29 The dummy gate structure 124 may be used to define the source/drain regions and the channel regions of the resulting semiconductor structure 10a ); depositing a first spacer layer ( Fig. 1K: spacer layers 136 ) over sidewalls of the interlayer dielectric structure in the opening ( as shown in Fig. 1K ); forming a silicide structure ( Col. 10 lines 53 – 59 a gate electrode layer may be formed over the work function layer 156. The gate electrode layer may be made of one or more layers of conductive material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, another suitable material, or a combination thereof ) over the source/drain epitaxial structures ( Fig. 1O #138 ); forming a bottom contact structure over the silicide structure ( Col. 10 lines 53 – 54 a gate electrode layer may be formed over the work function layer 156 ) ; depositing a second spacer layer ( Col. 7 lines 34 – 36 The spacer layers 136 may be multi-layer structures formed by different materials with different etching selectivity ) over the first spacer layer ( Fig. 1O #136 ); and forming an upper contact structure (Fig. 1E : dummy gate electrode layer 120 ) over the bottom contact structure ( Fig. 1J: dummy gate electrode layer 128; Col. 6 lines 31 - 34 the dummy gate electrode layer 128 may be replaced by the following steps to form a real gate structure with a high-k dielectric layer and a metal gate electrode layer ).
Regarding claim 2, Tsai teaches the method for forming the semiconductor device structure as claimed in claim 1 ( as discussed above), wherein the bottom contact structure ( Fig. 1K #128 ) is in direct contact with the first spacer layer ( Fig. 1K #136).
Regarding claim 3, Tsai teaches the method for forming the semiconductor device structure as claimed in claim 1 ( as discussed above), further comprising: removing the second spacer layer formed over the bottom contact structure ( Fig. 1K #128 ), wherein the bottom contact structure is recessed after removing the second spacer layer ( from Fig. 1M to Fig. 1N ).
Regarding claim 4, Tsai teaches the method for forming the semiconductor device structure as claimed in claim 1 ( as discussed above), further comprising: implanting dopants over the sidewalls ( Col. 9 lines 9 – 24 The ILD structure 140 may include multilayers made of multiple dielectric materials, such as silicon oxide (SiO.sub.x, where x may be a positive integer), silicon oxycarbide (SiCO.sub.y, where y may be a positive integer), silicon oxycarbonitride (SiNCO.sub.z, where z may be a positive integer), silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, or another applicable dielectric material. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. The ILD structure 140 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-on coating, or another applicable process ) of the interlayer dielectric structure ( Fig. 1M #140 ) in the opening to remove the second spacer layer formed over the sidewalls of the interlayer dielectric structure ( Col. 9 lines 25-34 Afterwards, a planarizing process or an etch-back process may be performed on the ILD structure 140 until the top surface of the dummy gate structure 124 is exposed. After the planarizing process, the top surface of the dummy gate structure 124 may be substantially level with the top surfaces of the spacer layers 136 and the ILD structure 140. The planarizing process may include a grinding process, a chemical mechanical polishing (CMP) process, an etching process, other applicable processes, or a combination thereof ).
Regarding claim 5, Tsai teaches the method for forming the semiconductor device structure as claimed in claim 4 ( as discussed above), wherein the second spacer layer ( Fig. 1M #136 ) remains over the source/drain epitaxial structures ( Col. 9 lines 6-8 After the contact etch stop layer 139 is formed, an inter-layer dielectric (ILD) structure 140 is formed over the source/drain epitaxial structure 138) after implanting the dopants over the sidewalls of the interlayer dielectric structure ( Fig. 1M #140 ).
Regarding claim 6, Tsai teaches the method for forming the semiconductor device structure as claimed in claim 4 ( as discussed above), wherein the first spacer layer ( Fig. 1M #136 ) remains over the sidewalls of the interlayer dielectric structure ( Fig. 1M #140 ) after the dopants are implanted over the sidewalls of the interlayer dielectric structure ( as shown in Fig. 1M ).
Regarding claim 8, Tsai teaches the method for forming the semiconductor device structure as claimed in claim 1 ( as discussed above), further comprising: forming a top contact structure ( Col 10 line 64- Col. 11 line 1 The wall structure 122 has a main portion 122m formed between the nanostructures 106 and an extending portion 122e laterally protruding out of the sidewalls of the nanostructures 106 ) over the upper contact structure in the opening ( Col. 5 lines 28-32 a wall structure material 122 may be formed in the opening 120 )
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under U.S.C. 103 as being unpatentable over Tsai et al.; US 12,538,533 B2; 02/2023 in view of Pan et al.; US 2024/0405021 A1; 09/2023
Claim 7: Tsai discloses the method for forming the semiconductor device structure as claimed in claim 4 ( as discussed above).
Tsai does not appear to disclose the first spacer layer is removed while implanting the dopants over the sidewalls of the interlayer dielectric structure
However, Pan teaches the first spacer layer is removed ( [0051] The bottom spacers 110/112 may be formed by conformally forming one or more dielectric material(s) over the semiconductor layers 102, the fin spacers 94, the gate spacers 92, the STI regions 70, and the masks 86 (if present) or the dummy gates 84, and then subsequently etching the dielectric material(s) ) while implanting the dopants over the sidewalls of the interlayer dielectric structure ( [0062] In FIGS. 15A-15C, a first ILD 124 is deposited over the epitaxial source/drain regions 118, the bottom spacers 112, the fin spacers 94, the gate spacers 92, and the masks 86 (if present) or the dummy gates 84).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Pan with Tsai to implement the first spacer layer is removed while implanting the dopants over the sidewalls of the interlayer dielectric structure because this approach precisely controls the doping profile, avoids shadowing effects, and optimizes the electrical characteristics of the device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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