DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention of Group I, Claims 1-16 and 21-24 in the reply filed on 02/04/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 11 and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. (US 2020/0105909).
Regarding claim 1, Wu et al. discloses, as shown in Figures 1-12B, a semiconductor device, comprising:
a substrate (40);
a nanostructured channel region (fin, 42) disposed on the substrate;
a gate structure (70) surrounding the nanostructured channel region;
a source/drain (S/D) region (54) disposed adjacent to the nanostructured channel region;
an etch stop layer (ESL) (58) disposed on the S/D region;
a stress liner (60a) disposed on the etch stop layer and configured to provide compressive stress in the nanostructured channel region;
an inter-layer dielectric (ILD) layer (64) disposed on the stress liner; and
a contact structure (78) disposed in the S/D region, ESL, stress liner, and ILD layer [0045]-[0052].
Regarding claim 11, Wu et al. discloses, as shown in Figures 1-12B, a semiconductor device comprising:
a substrate (40);
a fin structure (fin, 42) disposed on the substrate;
a gate structure (70) disposed on the fin structure;
a source/drain (S/D) region (54) disposed adjacent to the fin structure; and
a stack of dielectric layers (58,60a,64, etc.), disposed on the S/D region, comprising:
a first dielectric layer (58) disposed on the S/D region;
a second dielectric layer (60a) disposed on the first dielectric layer and configured to provide compressive stress in a fin region of the fin structure; and
a third dielectric layer (64) disposed on the second dielectric layer, wherein materials of the first, second, and third dielectric layers are different from each other [0045]-[0052].
Regarding claim 21, Wu et al. discloses, as shown in Figures 1-12B, a semiconductor device comprising:
a substrate (40);
a gate structure (70) disposed on the fin structure;
a source/drain (S/D) region (54) disposed adjacent to the gate structure;
a first silicon-based dielectric layer (58) disposed on the S/D region;
a germanium-based layer (60a) disposed on the first silicon-based dielectric layer; and
a second silicon-based dielectric layer (64) disposed on the germanium-based layer [0045]-[0052].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Colinge (US 2014/0312388) in view of Reference N (JP-4173672 B2).
Regarding claim 1, Colinge et al. discloses, as shown in Figures a semiconductor device, comprising:
a substrate (102);
a nanostructured channel region (fin, 106) disposed on the substrate;
a gate structure (302) surrounding the nanostructured channel region;
a source/drain (S/D) region (part of 106/108) disposed adjacent to the nanostructured channel region;
an inter-layer dielectric (ILD) layer (1202) disposed on the S/D region; and
a contact structure (1204,1206) disposed in the S/D region and ILD layer.
Colinge et al. does not disclose an etch stop layer (ESL) disposed on the S/D region, a stress liner disposed on the ESL and configured to provide compressive stress in the nanostructured channel region, and the contact structure disposed in the ESL and the stress liner. However, Reference N discloses a semiconductor device having an ESL (13) disposed on the S/D region, a stress liner (14b) disposed on the ESL and configured to provide compressive stress in the channel region, and the contact structure (19) disposed in the ESL and the stress liner. Note [0045]-[0051] and Figure 1 of Reference A. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the device of Colinge et al. having an etch stop layer (ESL) disposed on the S/D region, a stress liner disposed on the ESL and configured to provide compressive stress in the nanostructured channel region, and the contact structure disposed in the ESL and the stress liner, such as taught by Reference A, in order to increase the mobility of charges and enhance the performance of the transistors.
Regarding claim 11, Colinge et al. discloses, as shown in Figures, a semiconductor device comprising:
a substrate (102);
a fin structure (fin, 106) disposed on the substrate;
a gate structure (302) disposed on the fin structure;
a source/drain (S/D) region (part of 106/108) disposed adjacent to the fin structure. Colinge et al. does not disclose a stack of dielectric layers, disposed on the S/D region, comprising:
a first dielectric layer disposed on the S/D region;
a second dielectric layer disposed on the first dielectric layer and configured to provide compressive stress in a fin region of the fin structure; and
a third dielectric layer disposed on the second dielectric layer, wherein materials of the first, second, and third dielectric layers are different from each other. However, Reference A discloses a stack of dielectric layers (13,14b,16), disposed on the S/D region, comprising:
a first dielectric layer (13) disposed on the S/D region;
a second dielectric layer (14b) disposed on the first dielectric layer and configured to provide compressive stress in a channel; and
a third dielectric layer (16) disposed on the second dielectric layer, wherein materials of the first, second, and third dielectric layers are different from each other [0045]-[0051]. Note Figure 1 of Reference N. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the device of Colinge et al. having a stack of dielectric layers, such as taught by Reference A, in order to increase the mobility of charges and enhance the performance of the transistors.
Regarding claims 2-9 and 12-15, Colinge et al. and Reference N disclose all of the claimed limitations except material of the stress liner or the second dielectric layer. However, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the stress liner or the dielectric layer of Colinge et al. and Reference A having the materials as that claimed by Applicant, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claims 10 and 16, Colinge et al. and Reference N do not disclose the distance between the stress liner and a top surface of the nanostructure channel region, nor the thickness of the second dielectric layer. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, distance, thickness, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, distance, thickness, etc., or in combination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Alter 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Claim(s) 1-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Colinge (US 2014/0312388) in view of Grill et al. (US 2008/0303068).
Regarding claim 1, Colinge et al. discloses, as shown in Figures a semiconductor device, comprising:
a substrate (102);
a nanostructured channel region (fin, 106) disposed on the substrate;
a gate structure (302) surrounding the nanostructured channel region;
a source/drain (S/D) region (part of 106/108) disposed adjacent to the nanostructured channel region;
an inter-layer dielectric (ILD) layer (1202) disposed on the S/D region; and
a contact structure (1204,1206) disposed in the S/D region and ILD layer.
Colinge et al. does not disclose an etch stop layer (ESL) disposed on the S/D region, a stress liner disposed on the ESL and configured to provide compressive stress in the nanostructured channel region, and the contact structure disposed in the ESL and the stress liner. However, Grill et al. discloses a semiconductor device having a first layer (121, having a material that is capable to act as the etching stop layer) disposed on the S/D region (30’), a stress liner (122, 216, ta-C) disposed on the ESL and configured to provide compressive stress in the channel region, and the contact structure (223) disposed in the ESL and the stress liner. Note [0046]-[0051] and Figures 5-6 of Grill et al. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the device of Colinge et al. having an etch stop layer (ESL) disposed on the S/D region, a stress liner disposed on the ESL and configured to provide compressive stress in the nanostructured channel region, and the contact structure disposed in the ESL and the stress liner, such as taught by Grill et al., in order to increase the mobility of charges and enhance the performance of the transistors.
Regarding claims 2-9 and 12-15, Colinge et al. and Grill et al. disclose all of the claimed limitations except material of the stress liner or the second dielectric layer. However, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the stress liner or the dielectric layer of Colinge et al. and Reference A having the materials as that claimed by Applicant, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claims 10 and 16, Colinge et al. and Grill et al. do not disclose the distance between the stress liner and a top surface of the nanostructure channel region, nor the thickness of the second dielectric layer. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, distance, thickness, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, distance, thickness, etc., or in combination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Alter 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Regarding claim 11, Colinge et al. discloses, as shown in Figures, a semiconductor device comprising:
a substrate (102);
a fin structure (fin, 106) disposed on the substrate;
a gate structure (302) disposed on the fin structure;
a source/drain (S/D) region (part of 106/108) disposed adjacent to the fin structure. Colinge et al. does not disclose a stack of dielectric layers, disposed on the S/D region, comprising:
a first dielectric layer disposed on the S/D region;
a second dielectric layer disposed on the first dielectric layer and configured to provide compressive stress in a fin region of the fin structure; and
a third dielectric layer disposed on the second dielectric layer, wherein materials of the first, second, and third dielectric layers are different from each other. However, Grill et al. discloses a stack of dielectric layers (121,122,123,214,216,218), disposed on the S/D region, comprising:
a first dielectric layer (121,214) disposed on the S/D region;
a second dielectric layer (122,216) disposed on the first dielectric layer and configured to provide compressive stress in a channel; and
a third dielectric layer (123,218) disposed on the second dielectric layer, wherein materials of the first, second, and third dielectric layers are different from each other. Note [0046]-[0051] and Figures 5-6 of Grill et al. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the device of Colinge et al. having a stack of dielectric layers, such as taught by Grill et al., in order to increase the mobility of charges and enhance the performance of the transistors.
Claim(s) 2-10, 12-16, and 22-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2020/0105909).
Regarding claims 2-9, 12-15, and 22-24, Wu et al. discloses all of the claimed limitations except the material of the stress liner, the material of the second dielectric layer, or the material of the germanium-based layer. However, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the stress liner, the dielectric layer, or the germanium-based layer of Wu et al. having the materials as that claimed by Applicant, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claims 10 and 16, Wu et al. does not disclose the distance between the stress liner and a top surface of the nanostructure channel region, nor the thickness of the second dielectric layer. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, distance, thickness, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, distance, thickness, etc., or in combination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Alter 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Conclusion
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/HUNG K VU/ Primary Examiner, Art Unit 2897
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