DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Guo et al. (US 2019/0051524 A1 hereinafter referred to as “Guo”).
With respect to claim 1, Guo discloses, in Figs.1A-4B, a method comprising: forming a first insulation layer (312) on a first device component (310); forming a second insulation layer (322) on a second device component (320); performing a plasma activation process (360 and 360) to the first insulation layer (312) and the second insulation layer (322), wherein after the plasma activation process an upper portion (316 and 326) of the first insulation layer (312) and the second insulation layer (326) includes a plasma activated layer and a lower portion of the first insulation layer (312) and the second insulation layer (322) includes a barrier layer (see steps of Figs.3A-3B, Par.[0066] wherein front surface 312 of first wafer 310 and front surface 322 of second wafer 320 can include SiO.sub.2, Si.sub.3N.sub.4, or a nitrogen-doped silicon carbide; see Par.[0064]-[0065] wherein referring to FIG. 2 and FIG. 3A, method 200 starts at operation 202, in which plasma activation 360 is performed on front surface 312 of first wafer 310 and front surface 322 of second wafer 320; first wafer 310 and second wafer 320 can include silicon, germanium, a III-V semiconductor, silicon carbide, silicon on insulating substrate, or a combination thereof; ` first wafer 310 and second wafer 320 can include silicon (e.g., monocrystalline silicon, polycrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any suitable combination thereof; see Par.[0074] wherein as illustrated in FIG. 3B, front surface 312 of first wafer 310 and front surface 322 of second wafer 320 are exposed to a silica sol during the silica sol treatment to form first silica dielectric layer 316 on front surface 312 of first wafer 310 and second silica dielectric layer 326 on front surface 322 of second wafer 320); and bonding the plasma activated layers (316, 326) of respective ones of the first insulation layer (312) and the second insulation layer (322) to form a stacked structure that includes the first device component (310) over the second device component (320), wherein the first insulation layer (312) bonded to the second insulation layer (322) forms an isolation structure between the first device component (310) and the second device component (320) (see Par.[0085] wherein as illustrated in FIG. 3C, prior to the preliminary bonding process, first wafer 310 and second wafer 320 can be positioned in parallel and face to face with each other, with front surface 312 of first wafer 310 facing towards front surface 322 of second wafer 320).
With respect to claim 2, Guo discloses, in Figs.1A-4B, the method, wherein the first insulation layer (312) and the second insulation layer (322) include a single dielectric layer composed of silicon nitride (SiN) or silicon carbonitride (SiCN) (see steps of Figs.3A-3B, Par.[0066] wherein front surface 312 of first wafer 310 and front surface 322 of second wafer 320 can include SiO.sub.2, Si.sub.3N.sub.4, or a nitrogen-doped silicon carbide).
With respect to claim 3, Guo discloses, in Figs.1A-4B, the method, wherein the barrier layer includes a non-plasma treated portion of the single dielectric layer (see Step of Fig.3, Par.[0074] wherein as illustrated in FIG. 3B, front surface 312 of first wafer 310 and front surface 322 of second wafer 320 are exposed to a silica sol during the silica sol treatment to form first silica dielectric layer 316 on front surface 312 of first wafer 310 and second silica dielectric layer 326 on front surface 322 of second wafer 320. Respective first and second silica dielectric layers 316 and 326 can include SiO.sub.2 nanoparticles. In some embodiments, exposing the front surfaces of the first and second wafers can include performing a silica sol rinse on the front surfaces of the first and second wafers after one or more plasma activation treatments).
Claims 1-9, 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (US 2022/0293556 A1 hereinafter referred to as “Li”).
With respect to claim 1, Li discloses, in Figs.1A-18, a method comprising: forming a first insulation layer (304, 110) on a first device component (102a); forming a second insulation layer (304, 110) on a second device component (102b) (see Par.[0031] wherein the 2D ICs 116 are disposed in/over central regions 104 of the first and second semiconductor wafers 102a-b, respectively; see Par.[0042]-[0047] wherein bonding structure 304 includes dielectrics 426, 424, 422, 420, 418; see Par.[0050]-[0052] wherein the bonding support structure 110 may comprise a layer of dielectric material arranged along opposing sides of the plurality of stacked ILD layers 416 over the peripheral region 112 of the semiconductor wafer 102 such that the layer of dielectric material 416 may have an upper surface above or below the upper surface of the bonding structure 304; the bonding support structure 110 may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiON), a carbide (e.g., silicon carbide (SiC)), some other dielectric, or any combination of the foregoing); performing a plasma activation process to the first insulation layer (304) and the second insulation layer (304), wherein after the plasma activation process an upper portion/(upper plasma exclusion zone) of the first insulation layer (304) and the second insulation layer (304) includes a plasma activated layer and a lower portion of the first insulation layer (304) and the second insulation layer (304) includes a barrier layer/(non-plasma zone) (see Par.[0015], [0023], [0026], [0028], [0071], [0074] wherein during deposition of the first bonding support structure 304, an upper plasma exclusion zone (PEZ) ring is disposed over a front-side/(upper surface side of bonding structure) overlaying wafer 102; and the bonding support structure is selectively deposited by a plasma-enhanced CVD (PECVD)) of the first semiconductor wafer and a lower PEZ ring is disposed below a back-side of the first semiconductor wafer); and bonding the plasma activated layers of respective ones of the first insulation layer (304) and the second insulation layer (304) to form a stacked structure that includes the first device component (102a) over the second device component (102b), wherein the first insulation layer (304) bonded to the second insulation layer (304) forms an isolation structure between the first device component (102a) and the second device component (102b) (see steps of Figs.13-14, Par.[0080]-[0081] wherein after the deposition step (i.e.; Fig.13) the first semiconductor wafer 102a is bonded to a second semiconductor wafer 102b to form a 3D IC 302; the first semiconductor wafer 102a is bonded to the second semiconductor wafer 102b by bonding the interface dielectric layer 426, the conductive bonding link 428, and the bonding support structure 110 of the first semiconductor wafer 102a to a bonding interface dielectric layer 426, a conductive bonding link 428, and bonding support structure 110 of the second semiconductor wafer 102b, respectively).
With respect to claim 2, Li discloses, in Figs.1A-18, the method, wherein the first insulation layer (304, 110) and the second insulation layer (304, 110) include a single dielectric layer composed of silicon nitride (SiN) or silicon carbonitride (SiCN) (see Par.[0045]-[0046] wherein the redistribution dielectric layer 424 is a different material than the second etch stop layer 422 and may comprise, for example, an oxide (e.g., silicon dioxide), a low-k dielectric material, an ultra-low-k dielectric material, another dielectric material, or any combination of the foregoing; the bonding interface dielectric layer 426 is a different material than the redistribution dielectric layer 424 and may comprise, for example, silicon oxynitride, silicon nitride, silicon dioxide, another dielectric material, or any combination of the foregoing; see Par.[0052] wherein the bonding support structure 110 may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiON), a carbide (e.g., silicon carbide (SiC)), some other dielectric, or any combination of the foregoing).
With respect to claim 3, Li discloses, in Figs.1A-18, the method, wherein the barrier layer includes a non-plasma treated portion of the single dielectric layer (see Par.[0015], [0023], [0026], [0028], [0071], [0074] wherein during deposition of the first bonding support structure 304, an upper plasma exclusion zone (PEZ) ring is disposed over a front-side/(upper surface side of bonding structure) overlaying wafer 102; and the bonding support structure is selectively deposited by a plasma-enhanced CVD (PECVD)) of the first semiconductor wafer and a lower PEZ ring is disposed below a back-side of the first semiconductor wafer).
With respect to claim 4, Li discloses, in Figs.1A-18, the method, wherein the first insulation layer (304) and the second insulation layer (304) include a double dielectric layer, wherein a lower layer of the double dielectric layer is composed of silicon nitride (SiN) or silicon carbonitride (SiCN), and wherein an upper layer of the double dielectric layer is composed of silicon dioxide (SiO2) or silicon oxynitride (SiON) (see Par.[0045]-[0046] wherein the redistribution dielectric layer 424 is a different material than the second etch stop layer 422 and may comprise, for example, an oxide (e.g., silicon dioxide), a low-k dielectric material, an ultra-low-k dielectric material, another dielectric material, or any combination of the foregoing; the bonding interface dielectric layer 426 is a different material than the redistribution dielectric layer 424 and may comprise, for example, silicon oxynitride, silicon nitride, silicon dioxide, another dielectric material, or any combination of the foregoing; see Par.[0052] wherein the bonding support structure 110 may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiON), a carbide (e.g., silicon carbide (SiC)), some other dielectric, or any combination of the foregoing).
With respect to claim 5, Li discloses, in Figs.1A-18, the method, wherein the barrier layer includes the lower layer of the double dielectric layer and a non-plasma treated portion of the upper layer of the double dielectric layer (see Par.[0015], [0023], [0026], [0028], [0071], [0074] wherein during deposition of the first bonding support structure 304, an upper plasma exclusion zone (PEZ) ring is disposed over a front-side/(upper surface side of bonding structure) overlaying wafer 102; and the bonding support structure is selectively deposited by a plasma-enhanced CVD (PECVD)) of the first semiconductor wafer and a lower PEZ ring is disposed below a back-side of the first semiconductor wafer).
With respect to claim 6, Li discloses, in Figs.1A-18, the method, wherein the first insulation layer and the second insulation layer include a triple dielectric layer, wherein a bottom layer of the triple dielectric layer and a middle layer of the triple dielectric layer are composed of silicon nitride (SiN) or silicon carbonitride (SiCN), and wherein an upper layer of the triple dielectric layer is composed of silicon dioxide (SiO2) or silicon oxynitride (SiON) (see Par.[0045]-[0046] wherein the redistribution dielectric layer 424 is a different material than the second etch stop layer 422 and may comprise, for example, an oxide (e.g., silicon dioxide), a low-k dielectric material, an ultra-low-k dielectric material, another dielectric material, or any combination of the foregoing; the bonding interface dielectric layer 426 is a different material than the redistribution dielectric layer 424 and may comprise, for example, silicon oxynitride, silicon nitride, silicon dioxide, another dielectric material, or any combination of the foregoing; see Par.[0052] wherein the bonding support structure 110 may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiON), a carbide (e.g., silicon carbide (SiC)), some other dielectric, or any combination of the foregoing).
With respect to claim 7, Li discloses, in Figs.1A-18, the method, wherein the barrier layer includes the bottom layer of the triple dielectric layer, the middle layer of the triple dielectric layer, and a non-plasma treated portion of the upper layer of the triple dielectric layer (see Par.[0045]-[0046] wherein the redistribution dielectric layer 424 is a different material than the second etch stop layer 422 and may comprise, for example, an oxide (e.g., silicon dioxide), a low-k dielectric material, an ultra-low-k dielectric material, another dielectric material, or any combination of the foregoing; the bonding interface dielectric layer 426 is a different material than the redistribution dielectric layer 424 and may comprise, for example, silicon oxynitride, silicon nitride, silicon dioxide, another dielectric material, or any combination of the foregoing; see Par.[0052] wherein the bonding support structure 110 may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiON), a carbide (e.g., silicon carbide (SiC)), some other dielectric, or any combination of the foregoing).
With respect to claim 8, Li discloses, in Figs.1A-18, the method, wherein the bottom layer and the middle layer of the triple dielectric layer are the same (see Par.[0045]-[0046] wherein the redistribution dielectric layer 424 is a different material than the second etch stop layer 422 and may comprise, for example, an oxide (e.g., silicon dioxide), a low-k dielectric material, an ultra-low-k dielectric material, another dielectric material, or any combination of the foregoing; the bonding interface dielectric layer 426 is a different material than the redistribution dielectric layer 424 and may comprise, for example, silicon oxynitride, silicon nitride, silicon dioxide, another dielectric material, or any combination of the foregoing; see Par.[0052] wherein the bonding support structure 110 may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiON), a carbide (e.g., silicon carbide (SiC)), some other dielectric, or any combination of the foregoing).
With respect to claim 9, Li discloses, in Figs.1A-18, the method, wherein the bottom layer and the middle layer of the triple dielectric layer are different (see Par.[0045]-[0046] wherein the redistribution dielectric layer 424 is a different material than the second etch stop layer 422 and may comprise, for example, an oxide (e.g., silicon dioxide), a low-k dielectric material, an ultra-low-k dielectric material, another dielectric material, or any combination of the foregoing; the bonding interface dielectric layer 426 is a different material than the redistribution dielectric layer 424 and may comprise, for example, silicon oxynitride, silicon nitride, silicon dioxide, another dielectric material, or any combination of the foregoing; see Par.[0052] wherein the bonding support structure 110 may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiON), a carbide (e.g., silicon carbide (SiC)), some other dielectric, or any combination of the foregoing).
With respect to claim 18, Li discloses, in Figs.1A-18, a semiconductor device comprising: a transistor stack having a first transistor (116) disposed over a second transistor (312), wherein: the first transistor (116) has first semiconductor layers (402), a first gate stack, and first source/drains (404), wherein the first semiconductor layers are disposed between the first source/drains, the first gate stack is disposed between the first source/drains and wraps the first semiconductor layers, the second transistor has second semiconductor layers, a second gate stack, and second source/drains, wherein the second semiconductor layers are disposed between the second source/drains, the second gate stack is disposed between the second source/drains and wraps the second semiconductor layers, and the first source/drains are disposed over the second source/drains and the first gate stack is disposed over the second gate stack (see Par.[0039] wherein a 2D IC 116 comprises a plurality of semiconductor devices 402 (e.g., transistors). In some embodiments, each of the semiconductor devices 402 comprise a pair of source/drain regions 404 disposed in the semiconductor wafer 102); and an insulation layer (304) disposed between the first gate stack and the second gate stack, wherein the insulation layer includes bonding layer portions having plasma activated layers and barrier layer portions interposing the bonding layer portions and respective ones of the first gate stack and the second gate stack (see Par.[0015], [0023], [0026], [0028], [0071], [0074] wherein during deposition of the first bonding support structure 304, an upper plasma exclusion zone (PEZ) ring is disposed over a front-side/(upper surface side of bonding structure) overlaying wafer 102; and the bonding support structure is selectively deposited by a plasma-enhanced CVD (PECVD)) of the first semiconductor wafer and a lower PEZ ring is disposed below a back-side of the first semiconductor wafer; see steps of Figs.13-14, Par.[0080]-[0081] wherein after the deposition step (i.e.; Fig.13) the first semiconductor wafer 102a is bonded to a second semiconductor wafer 102b to form a 3D IC 302; the first semiconductor wafer 102a is bonded to the second semiconductor wafer 102b by bonding the interface dielectric layer 426, the conductive bonding link 428, and the bonding support structure 110 of the first semiconductor wafer 102a to a bonding interface dielectric layer 426, a conductive bonding link 428, and bonding support structure 110 of the second semiconductor wafer 102b, respectively).
With respect to claim 19, Li discloses, in Figs.1A-18, the semiconductor device, wherein the plasma activated layers include plasma activated portions of silicon dioxide (SiO2) layers or silicon oxynitride (SiON) layers (see Par.[0045]-[0046] wherein the redistribution dielectric layer 424 is a different material than the second etch stop layer 422 and may comprise, for example, an oxide (e.g., silicon dioxide), a low-k dielectric material, an ultra-low-k dielectric material, another dielectric material, or any combination of the foregoing; the bonding interface dielectric layer 426 is a different material than the redistribution dielectric layer 424 and may comprise, for example, silicon oxynitride, silicon nitride, silicon dioxide, another dielectric material, or any combination of the foregoing; see Par.[0052] wherein the bonding support structure 110 may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiON), a carbide (e.g., silicon carbide (SiC)), some other dielectric, or any combination of the foregoing).
With respect to claim 20, Li discloses, in Figs.1A-18, the semiconductor device, wherein the barrier layer portions include silicon nitride (SiN) or silicon carbonitride (SiCN) (see Par.[0045]-[0046] wherein the redistribution dielectric layer 424 is a different material than the second etch stop layer 422 and may comprise, for example, an oxide (e.g., silicon dioxide), a low-k dielectric material, an ultra-low-k dielectric material, another dielectric material, or any combination of the foregoing; the bonding interface dielectric layer 426 is a different material than the redistribution dielectric layer 424 and may comprise, for example, silicon oxynitride, silicon nitride, silicon dioxide, another dielectric material, or any combination of the foregoing; see Par.[0052] wherein the bonding support structure 110 may comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxy-nitride (e.g., SiON), a carbide (e.g., silicon carbide (SiC)), some other dielectric, or any combination of the foregoing).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-17 are rejected under 35 U.S.C. 103 as being unpatentable over Katkar (US 2022/0328521 A1) in view of Guo.
With respect to claim 10, Katkar discloses, in Figs.4A-11, a method comprising: forming a first insulation layer (403) on a first substrate (405) including a first superlattice structure/(alternative layers) or a first transistor channel layer; forming a second insulation layer (404) on a second substrate (406) including a second superlattice structure or a second transistor channel layer (see Par.[0041] wherein see Par.[0045]-[0046] wherein the sub-stacks may be formed of uniform, alternating layers of material typically used in a memory pyramid, such as silicon oxide and silicon nitride, silicon oxide and polysilicon, or other such alternating layers of materials; a conventional 64 layer stack would comprise of 64 alternating layers of silicon oxide and silicon nitride each or 64 alternating layers of silicon oxide and polysilicon each sub-stacks 403 and 404 formed on carrier substrates 405 and 406, respectively and comprising illustrates silicon nitride to be the first layer deposited on either carriers 405 and 406, the first layer may also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, polysilicon or any other dielectric layer; although FIG. 4A illustrates the exposure of silicon nitride layer 409 after carrier substrate 405 was removed, the exposed layer could be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, polysilicon or any other layer deposited in the stack). However, Katkar does not explicitly disclose that performing a plasma activation process to the first insulation layer and the second insulation layer to form a plasma activated layer having a plasma activated surface within each of the first and second insulation layers, wherein non-plasma treated portions of the first and second insulation layers include a barrier layer; contacting the plasma activated surfaces of the first and second insulation layers; and performing an annealing process to bond the contacted plasma activated surfaces to form a stacked structure including a bonding layer between the first substrate and the second substrate, wherein the bonding layer isolates the first substrate from the second substrate.
Guo discloses, in Figs.1A-4B, a method comprising: forming a first insulation layer (312) on a first substrate (310) including a first superlattice structure or a first transistor channel layer; forming a second insulation layer (322) on a second substrate (320) including a second superlattice structure or a second transistor channel layer; performing a plasma activation process to the first insulation layer (312) and the second insulation layer (322) to form a plasma activated layer having a plasma activated surface within each of the first and second insulation layers, wherein non-plasma treated portions of the first and second insulation layers include a barrier layer; contacting the plasma activated surfaces of the first and second insulation layers (see steps of Figs.3A-3B, Par.[0066] wherein front surface 312 of first wafer 310 and front surface 322 of second wafer 320 can include SiO.sub.2, Si.sub.3N.sub.4, or a nitrogen-doped silicon carbide; see Par.[0064]-[0065] wherein referring to FIG. 2 and FIG. 3A, method 200 starts at operation 202, in which plasma activation 360 is performed on front surface 312 of first wafer 310 and front surface 322 of second wafer 320; first wafer 310 and second wafer 320 can include silicon, germanium, a III-V semiconductor, silicon carbide, silicon on insulating substrate, or a combination thereof; ` first wafer 310 and second wafer 320 can include silicon (e.g., monocrystalline silicon, polycrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any suitable combination thereof; see Par.[0074] wherein as illustrated in FIG. 3B, front surface 312 of first wafer 310 and front surface 322 of second wafer 320 are exposed to a silica sol during the silica sol treatment to form first silica dielectric layer 316 on front surface 312 of first wafer 310 and second silica dielectric layer 326 on front surface 322 of second wafer 320; see Par.[0085] wherein as illustrated in FIG. 3C, prior to the preliminary bonding process, first wafer 310 and second wafer 320 can be positioned in parallel and face to face with each other, with front surface 312 of first wafer 310 facing towards front surface 322 of second wafer 320; the idea of having: a first insulation layer on a first substrate including a first superlattice structure or a first transistor channel layer; forming a second insulation layer on a second substrate including a second superlattice structure or a second transistor channel layer is borrowed from Katkar); and performing an annealing process to bond the contacted plasma activated surfaces to form a stacked structure including a bonding layer between the first substrate (310) and the second substrate (320), wherein the bonding layer isolates the first substrate from the second substrate (see Par.[0094] wherein the heat treatment can include thermally annealing the first and the second wafers after bonding; the bonded first and second wafers are thermally annealed under nitrogen atmosphere, with an annealing temperature between about 200° C. and 450° C).
Katkar and Guo are analogous art because they are all directed to a semiconductor wafer bonding method, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Katkar to include Guo because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the bonding method in Katkar by including plasma activation of upper portion of upper bonding insulating layers follow by annealing as taught by Guo in order to utilize the advantages offered by the pre-bonding two consecutive steps (i.e.; surface plasma-activation followed by anneal) such as: lower processing temperatures; enhanced bonding strength; no intermediate layering needed; prevention of bonding defects and/or high fracture toughness.
With respect to claim 11, Guo discloses, in Figs.1A-4B, the method, wherein the first insulation layer and the second insulation layer include a single dielectric layer, a double dielectric layer, or a triple dielectric layer (see steps of Figs.3A-3B, Par.[0066] wherein front surface 312 of first wafer 310 and front surface 322 of second wafer 320 can include SiO.sub.2, Si.sub.3N.sub.4, or a nitrogen-doped silicon carbide).
With respect to claim 11, Katkar discloses, in Figs.4A-11, the method, wherein the first insulation layer (503) and the second insulation layer (504) include a single dielectric layer, a double dielectric layer, or a triple dielectric layer (see Par.[0041] wherein see Par.[0045]-[0046] wherein the sub-stacks may be formed of uniform, alternating layers of material typically used in a memory pyramid, such as silicon oxide and silicon nitride, silicon oxide and polysilicon, or other such alternating layers of materials; a conventional 64 layer stack would comprise of 64 alternating layers of silicon oxide and silicon nitride each or 64 alternating layers of silicon oxide and polysilicon each sub-stacks 403 and 404 formed on carrier substrates 405 and 406, respectively and comprising illustrates silicon nitride to be the first layer deposited on either carriers 405 and 406, the first layer may also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, polysilicon or any other dielectric layer; although FIG. 4A illustrates the exposure of silicon nitride layer 409 after carrier substrate 405 was removed, the exposed layer could be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, polysilicon or any other layer deposited in the stack).
With respect to claim 12, Katkar discloses, in Figs.4A-11, the method, wherein the single dielectric layer includes silicon nitride (SiN) or silicon carbonitride (SiCN) (see Par.[0041] wherein see Par.[0045]-[0046] wherein the sub-stacks may be formed of uniform, alternating layers of material typically used in a memory pyramid, such as silicon oxide and silicon nitride, silicon oxide and polysilicon, or other such alternating layers of materials; a conventional 64 layer stack would comprise of 64 alternating layers of silicon oxide and silicon nitride each or 64 alternating layers of silicon oxide and polysilicon each sub-stacks 403 and 404 formed on carrier substrates 405 and 406, respectively and comprising illustrates silicon nitride to be the first layer deposited on either carriers 405 and 406, the first layer may also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, polysilicon or any other dielectric layer; although FIG. 4A illustrates the exposure of silicon nitride layer 409 after carrier substrate 405 was removed, the exposed layer could be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, polysilicon or any other layer deposited in the stack).
With respect to claim 13, Katkar discloses, in Figs.4A-11, the method, wherein the double dielectric layer includes a lower layer composed of silicon nitride (SiN) or silicon carbonitride (SiCN) and an upper layer composed of silicon dioxide (SiO2) or silicon oxynitride (SiON) (see Par.[0041] wherein see Par.[0045]-[0046] wherein the sub-stacks may be formed of uniform, alternating layers of material typically used in a memory pyramid, such as silicon oxide and silicon nitride, silicon oxide and polysilicon, or other such alternating layers of materials; a conventional 64 layer stack would comprise of 64 alternating layers of silicon oxide and silicon nitride each or 64 alternating layers of silicon oxide and polysilicon each sub-stacks 403 and 404 formed on carrier substrates 405 and 406, respectively and comprising illustrates silicon nitride to be the first layer deposited on either carriers 405 and 406, the first layer may also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, polysilicon or any other dielectric layer; although FIG. 4A illustrates the exposure of silicon nitride layer 409 after carrier substrate 405 was removed, the exposed layer could be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, polysilicon or any other layer deposited in the stack).
With respect to claim 14, Katkar discloses, in Figs.4A-11, the method, wherein the triple dielectric layer includes a bottom layer and a middle layer composed of silicon nitride (SiN) or silicon carbonitride (SiCN) and an upper layer composed of silicon dioxide (SiO2) or silicon oxynitride (SiON) (see Par.[0041] wherein see Par.[0045]-[0046] wherein the sub-stacks may be formed of uniform, alternating layers of material typically used in a memory pyramid, such as silicon oxide and silicon nitride, silicon oxide and polysilicon, or other such alternating layers of materials; a conventional 64 layer stack would comprise of 64 alternating layers of silicon oxide and silicon nitride each or 64 alternating layers of silicon oxide and polysilicon each sub-stacks 403 and 404 formed on carrier substrates 405 and 406, respectively and comprising illustrates silicon nitride to be the first layer deposited on either carriers 405 and 406, the first layer may also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, polysilicon or any other dielectric layer; although FIG. 4A illustrates the exposure of silicon nitride layer 409 after carrier substrate 405 was removed, the exposed layer could be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, polysilicon or any other layer deposited in the stack).
With respect to claim 15, Guo discloses, in Figs.1A-4B, the method, wherein the plasma activation process is an oxygen plasma treatment (see Par.[0068]-[0072] wherein plasma gases used in the plasma activation includes, but not limited to, oxygen, nitrogen, argon or a combination thereof; in some embodiments, the plasma gas can be oxygen; in some embodiments, the plasma gas can be nitrogen. In some embodiments, the plasma gas can further include other gases such as hydrogen and/or water).
With respect to claim 16, Guo discloses, in Figs.1A-4B, the method, wherein the plasma activated surface includes OH- dangling bonds (see Par.[0059]-[0061] wherein first wafer 110 and second wafer 120 are positioned face to face with front surface 112 of first wafer 110 facing towards front surface 122 of second wafer 120, with a layer of hydroxyl groups OH- in between; after the heat treatment, covalent bond Si—O—Si forms in interface layer 135 between front surface 112 of first wafer 110 and front surface 122 of second wafer 120, bonding the two wafers together).
With respect to claim 17, Guo discloses, in Figs.1A-4B, the method, wherein the performing the annealing process to bond the contacted plasma activated surfaces forms at least one of Si-C-Si bonds and Si-O-Si bonds between the plasma activated layers of respective ones of the first insulation layer and the second insulation layer (see Par.[0059]-[0061] wherein first wafer 110 and second wafer 120 are positioned face to face with front surface 112 of first wafer 110 facing towards front surface 122 of second wafer 120, with a layer of hydroxyl groups OH- in between; after the heat treatment, covalent bond Si—O—Si forms in interface layer 135 between front surface 112 of first wafer 110 and front surface 122 of second wafer 120, bonding the two wafers together).
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
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