DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending.
Claims 1, 3, 9, 10, and 15-17 are amended.
Drawings
The objections to the drawings of 03/26/2026 have been overcome by the amended drawings filed 06/24/2026. The objections are withdrawn.
Claim Objections
The objections to claims 3, 9, and 16 of 03/26/2026 have been overcome by the amended claims filed 06/24/2026. The objections are withdrawn.
Response to Arguments
Applicant's arguments filed 06/08/2026 have been fully considered but they are not persuasive. Specifically, amendment of the independent claims to include the claim language “wherein the corner of the seal ring region includes the upper metallization layer of the at least one stack of the MLI” does not overcome the prior art rejection of record. Liang (US Patent 9,627,332) teaches wherein the corner of the seal ring region includes the upper metallization layer of the at least one stack of the MLI, shown in at least Fig. 1B. Additionally, applicant’s arguments, pages 9-12, regarding the rejection of amended independent claims 1 and 10 are not persuasive. Specifically, applicant argues against the combination of Liang in view of Chen (US PGPub 2016/0071779), however, the feature of Chen, wherein the redistribution layer is absent from a corner region of the device of Liang would not render the device of Liang inoperable, as the pad ring of Liang could be shaped in a way in order to provide for a closed-loop structure, maintaining protection within the looped feature, and this would be considered in design of such a device. The rejections of claims 1-14 are maintained.
Applicants arguments, pages 9-12, regarding the rejection of amended independent claim 15 are persuasive. Specifically, inclusion of the claim language “and is excluded from corner portions of the seal ring region” overcomes the prior art rejection of record. A new grounds of rejection is made further in view of Chen.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-13, 15, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Liang in view of Chen et al. (US PGPub 2016/0071779; herein known as Chen).
Regarding claim 1, Liang teaches (Figs. 1A-C) a semiconductor structure, comprising: a substrate (10, [Col 2, Line 31]) having a circuit region (10A, [Col 2, Line 54]) and a seal ring region (10S, [Col 2, Line 54]) around the circuit region; at least one stack of a multi-layer interconnect (MLI) (42, 44, 46, [Col 3, Lines 40-60]) extending from the substrate to an upper metallization layer (54, [Col 6, Line 18]) in the seal ring region, wherein the at least one stack is continuous (shown in Fig. 1A) around the circuit region in a top view; and a redistribution layer (64, [Col 6, Line 42]) disposed over the upper metallization layer, wherein the redistribution layer extends along a lateral side of the seal ring region (Fig. 1A) and wherein the corner of the seal ring region (10S) includes the upper metallization layer (54) of the at least one stack of the MLI (42, 44, 46).
Liang does not explicitly teach wherein a corner of the seal ring region is devoid of the redistribution layer.
Chen teaches (Fig. 5) wherein a corner of the seal ring region (510-516, [0050]) is devoid of the redistribution layer (104, [0016]).
Because Liang and Chen are both directed toward RDL layers surrounding active regions, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Liang and Chen to include wherein a corner of the seal ring region is devoid of the redistribution layer in order to reduce or prevent delamination between the molding layer and redistribution layers (Chen, [0016]).
Regarding claim 2, Liang in view of Chen teaches the semiconductor structure of claim 1, but does not explicitly teach further comprising: at least one transistor formed in the circuit region; and another stack of the MLI disposed over and connected to the at least one transistor.
Chen further teaches: at least one transistor formed in the circuit region (312, [0032]) formed in the circuit region (102, [0016]); and another stack of the MLI (340a, [0038]) disposed over and connected to the at least one transistor ([0038]).
Because Liang and Chen are both directed toward RDL layers surrounding active regions, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine the teachings of Liang and Chen to include at least one transistor formed in the circuit region; and another stack of the MLI disposed over and connected to the at least one transistor to provide connection between an inner die and outer packaging through known packaging methods (Chen, [0021]).
Regarding claim 3, Liang in view of Chen teaches (Liang, Fig. 1A) the semiconductor structure of claim 1, wherein the seal ring region (10S, [Col 2, Line 54]) is substantially rectangular in shape in a top view (shown in Fig. 1A).
Regarding claim 4, Liang in view of Chen teaches (Liang, annotated Fig. 1A below) the semiconductor structure of claim 3, wherein the redistribution layer (64, [Col 6, Line 42]) is disposed on a first side (S1) of the substantially rectangular shape and a second side (S2) of the substantially rectangular shape, the corner (C1) disposed between the first side and the second side.
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Regarding claim 5, Liang in view of Chen teaches (Chen, Fig. 2) the semiconductor structure of claim 4, wherein the corner devoid of the redistribution layer (104) has a first length (D2, [0024]) extending to the first side, wherein the corner devoid of the redistribution layer has a second length (D3, [0024]) extending to the second side, wherein the first and second lengths are at least 50 microns ([0024]).
Regarding claim 6, Liang in view of Chen teaches (Chen, Fig. 2) the semiconductor structure of claim 3, wherein the redistribution layer (104, [0018]) has a terminal end (interpreted as the corner edge of the RDL layer) in the top view, wherein the terminal end is at least 50 microns from a corner of the seal ring region ([0024]).
Regarding claim 7, Liang in view of Chen teaches (Liang, annotated Fig. 1A below) the semiconductor structure of claim 3, wherein the redistribution layer (64, [Col 6, Line 42]) is disposed on a first side (S1) of the substantially rectangular shape and a second side (S2) of the substantially rectangular shape, the first side opposing the second side in the top view.
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Regarding claim 9, Liang in view of Chen teaches (Liang, Fig. 1B) the semiconductor structure of claim 1, further comprising: a protection layer (68, [Col 7, Line 4]) over the redistribution layer (64, [Col 6, Line 42]).
Regarding claim 10, Liang teaches (annotated Fig. 1A below, Fig. 1B) a semiconductor structure, comprising: a substrate (10, [Col 2, Line 31]) having a circuit region (10A, [Col 2, Line 54]); a seal ring structure (30, [Col 2, Line 54]) comprising a plurality of metallization layers (42, 44, 46, [Col 3, Lines 40-60]), the seal ring structure surrounding the circuit region in a top view such that the seal ring structure is disposed along a first side (S1) of the circuit region, a second side (S2) of the circuit region and a corner (C1) of the circuit region between the first side and the second side; a first element (64) of a redistribution layer disposed over the seal ring structure disposed along the first side of the circuit region; a second element of the redistribution layer (64, [Col 6, Line 42]) disposed over the seal ring structure disposed along the second side of the circuit region; and a passivation layer (62) extending from the second element in the corner of the circuit region between the first side and the second side.
Liang does not explicitly teach wherein no element of the redistribution layer is disposed over the seal ring structure disposed along the corner of the circuit region.
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Chen teaches (Fig. 5) wherein no element of the redistribution layer (104, [0016]) is disposed over the seal ring structure disposed along the corner (510-516, [0050]) of the circuit region ([0016]).
Because Liang and Chen are both directed toward RDL layers surrounding active regions, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Liang and Chen to include wherein a corner of the seal ring region is devoid of the redistribution layer in order to reduce or prevent delamination between the molding layer and redistribution layers (Chen, [0016]).
Regarding claim 11, Liang in view of Chen teaches (Liang, annotated Fig. 1B below) the semiconductor structure of claim 10, further comprising: a via (Via) extending from the first element of the redistribution layer (64, [Col 6, Line 42]) to an uppermost metallization layer (54, [Col 6, Line 18]) of the seal ring structure (30, [Col 3, Line 4]).
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Regarding claim 12, Liang in view of Chen teaches (Liang, annotated Fig. 1B above) the semiconductor structure of claim 11, a passivation layer (68, [Col 7, Line 4]) formed adjacent the via (Via) and adjacent the redistribution layer (64, [Col 6, Line 42]).
Regarding claim 13, Liang in view of Chen teaches (Liang, Fig. 1B) the semiconductor structure of claim 12, wherein the passivation layer (68, [Col 7, Line 4]) interfaces an entirety of an uppermost surface of the seal ring structure (30, [Col 3, Line 4]) disposed at the corner of the circuit region (shown to cover entirety of seal ring structure).
Regarding claim 15, Liang teaches (Figs. 1A-1C) a method of fabricating a semiconductor structure, comprising: providing a semiconductor substrate (10, [Col 2, Line 31]) having a circuit region (10A, [Col 2, Line 54]) and a seal ring region (10S, [Col 2, Line 54]); forming an active device (11, [Col 2, Line 55]) in the circuit region; forming a multi-layer interconnect (MLI) (42, 44, 46, [Col 3, Lines 40-60]) over the semiconductor substrate, a first stack of the MLI forming an interconnection to the active device (not shown, [Col 3, Lines 4-7]) and a second stack of the MLI forming a seal ring structure (30, [Col 3, Line 4]) surrounding the circuit region; after forming the MLI, depositing a passivation layer (62, [Col 6, Line 40]) over the MLI; forming a redistribution layer (64, [Col 6, Line 42]) over the passivation layer, wherein the forming the redistribution layer includes: depositing a conductive material ([Col 6, Line 44]) ; and patterning the conductive material ([Col 3, Line 67]) such that it is disposed only at a lateral side of the seal ring region (Fig. 1A); and depositing a protective layer (68, [Col 7, Line 4]) over the redistribution layer.
Liang does not explicitly teach and is excluded from corner portions of the seal ring region.
Chen teaches (Fig. 5) wherein a corner of the seal ring region (510-516, [0050]) is devoid of the redistribution layer (104, [0016]).
Because Liang and Chen are both directed toward RDL layers surrounding active regions, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Liang and Chen to include wherein and is excluded from corner portions of the seal ring region in order to reduce or prevent delamination between the molding layer and redistribution layers (Chen, [0016]).
Regarding claim 19, Liang in view of Chen teaches (Fig. 1B) the method of claim 15, wherein the forming the MLI (42, 44, 46, [Col 3, Lines 40-60]) includes forming a stack of conductive vias (46, [Col 3, Line 53]) alternating between conductive lines (44, [Col 3, Line 46]), and depositing dielectric materials (42, [Col 3, Line 66]) around the stack.
Regarding claim 20, Liang in view of Chen teaches the method of claim 15, wherein the depositing the protective layer includes spin coating a polyimide (Chen, [0040]).
Claims 8 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Liang in view of Chen as applied to claims 7 and 11 above, further in view of Huang et al. (US PGPub 2022/0277127; herein known as Huang).
Regarding claim 8, Liang in view of Chen teaches the semiconductor structure of claim 7, but does not explicitly teach wherein the redistribution layer on the first side is a plurality of segments in the top view and the redistribution layer on the second side is a continuous line in the top view, the continuous line being longer than the plurality of segments.
The instant application teaches wherein the design of the redistribution layer can be chosen in order to modify the stresses in the wafer upon sawing.
Huang teaches wherein the redistribution layer can be continuous or can have a pattern separated by spaces ([0050]), with the predictable outcome of changing the speed of the bonding wave the wafer in the direction of the RDL, thus impacting the stresses in the wafer.
Because Liang in view of Chen and Huang are both directed toward RDL seal rings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the RDL structure of Liang in view of Chen with the teachings of Huang in order to obtain the predictable result of changing the speed of the bonding wave of the wafer along the modified RDL side, and thus modifying the stresses in the wafer. Absent a teaching of criticality of the claimed subject matter, it would have thus been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include wherein the redistribution layer on the first side is a plurality of segments in the top view and the redistribution layer on the second side is a continuous line in the top view, the continuous line being longer than the plurality of segments to achieve that predictable result. See MPEP 2143.I.B.
Regarding claim 14, Liang in view of Chen teaches the semiconductor structure of claim 11, but does not explicitly teach wherein the first element of the redistribution layer and the second element of the redistribution layer are asymmetrical.
Huang teaches wherein the first element of the redistribution layer and the second element of the redistribution layer are asymmetrical. ([0050]).
The instant application teaches wherein the design of the redistribution layer can be chosen in order to modify the stresses in the wafer upon sawing.
Because Liang in view of Chen and Huang are both directed toward RDL seal rings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the RDL structure of Liang in view of Chen with the teachings of Huang in order to obtain the predictable result of changing the speed of the bonding wave of the wafer along the modified RDL side, and thus modifying the stresses in the wafer. Absent a teaching of criticality of the claimed subject matter, it would have thus been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include teach wherein the first element of the redistribution layer and the second element of the redistribution layer are asymmetrical for that predictable result. See MPEP 2143.I.B.
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Liang in view of Chen as applied to claim 15 above, and as evidenced by Shauly (Design Rules in a Semiconductor Foundry, 2022; herein known as Shauly, provided for reference).
Regarding claim 16, Liang as evidenced by Shauly teaches the method of claim 15, further comprising: designing a pattern layout including defining: circuit patterns for the circuit region; interconnect patterns providing the first stack in the circuit region and the second stack in the seal ring region including in corner portions of the seal ring region; and redistribution layers for the circuit region and the seal ring region,
Pattern design is known in the art as a requirement for fabrication and manufacture of semiconductor devices, examples of which are evidenced by Shauly. In order to fabricate a semiconductor structure, one must necessarily design a pattern layout, and if that device includes a circuit region, interconnects, and a redistribution layer, those regions must necessarily be designed accordingly.
Liang as evidenced by Shauly does not explicitly teach wherein the pattern layout for the redistribution layers excludes the redistribution layer from corner portions the seal ring region.
Chen teaches wherein the pattern layout for the redistrubution layers excludes the redistribution layer from corner portions (510-516, [0050]) of the seal ring region ([0016]).
Because Liang as evidenced by Shauly and Chen are both directed toward RDL layers surrounding active regions, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Liang as evidenced by Shauly and of Chen to include wherein the pattern layout for the redistribution layers excludes the redistribution layer from corner portions the seal ring region in order to reduce or prevent delamination between the molding layer and redistribution layers (Chen, [0016]).
Regarding claim 17, Liang in view of Chen and as evidenced by Shauly teaches the method of claim 16, wherein the designing the pattern layout includes implementing a design rule to exclude the redistribution layers from corner portions the seal ring region and including interconnect patterns in corner portions of the seal ring region (Chen, [0016]).
Regarding claim 18, Liang in view of Chen and as evidenced by Shauly teaches the method of claim 17, wherein the design rule excludes at least 50 microns of length adjacent the corner from including the redistribution layer (Chen, [0024]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EMILY FARMER/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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