DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed on 11/18/2025 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of any patent granted on Application Number 17/883,584 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-2, 4-6 and 14-21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Re claim 1, the phrase “the first portion of the GaN layer is in a range of 300 and 1500 nanometers” was not described in the original specification.
Re claims 6 and 20, the phrase “AlyGa1-yN where 0≤y≤1” was not described in the original specification (i.e., 0=y=1).
Re claim 14, the phrase “the third GaN layer being formed to have a third resistivity that is lower than the first resistivity” was not described in the original specification. Note: paragraph 25 of the instant specification appears to indicate the second GaN layer 208A (NOT third GaN 208b) has a lower resistivity than the transition layer 204.
Re claim 21, the phrase “wherein the third resistivity of the third GaN layer is lower than the first resistivity of the first GaN layer” was not described in the original specification.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Re claim 6, the phrase “the Si substrate is polished to have a surface orientation of<111>” does not positively recite the active processing step.
Re claim 7, line 3, the phrase “over a buffer layer that is formed” does not positively recite the active processing step.
Re claim 7, lines 4, 5-6, and 11, the phrase “first GaN layer is formed to have a first resistivity” or “second GaN layer is formed to have a second resistivity, wherein the first resistivity is higher than the second resistivity” or “third GaN layer is formed to have a third resistivity” is unclear and indefinite (i.e., how? Since they are the exact same material, Ga1N1 for first, second and third layers) and the above phrase also does not positively recite the active processing step.
Re claim 14, line 3, the phrase “over a buffer layer that is formed a substrate” is unclear and indefinite. It also does not positively recite the active processing step.
Re claim 14, lines 4, 5-6, and 8-9, the phrase “first GaN layer being formed to have a first resistivity” or “second GaN layer being formed to have a second resistivity that is lower than the first resistivity” or “third GaN layer being formed to have a third resistivity that is lower than the first resistivity” is unclear and indefinite (i.e., how? Since they are the exact same material, Ga1N1 for first, second and third layers) and the above phrase also does not positively recite the active processing step.
Re claim 20, the phrase “the substrate is polished to have a surface orientation of <111>” does not positively recite the active processing step.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 7-9, 11-12, 14-15 and 17-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al., WO-2017/000906 A1.
Re claim 7, Chen et al. disclose a method for manufacturing a High Electron Mobility Transistor, comprising: forming a first Gallium Nitride (GaN) layer 406 over a buffer layer 404 that is formed over a substrate 402 (fig. 4), wherein the first GaN layer is formed to have a first resistivity (fig. 4, paragraph 42 i.e., this is intrinsic properties of the material); forming a second GaN layer 408b (fig. 4) over the first GaN layer, wherein the second GaN layer is formed to have a second resistivity (i.e., fig. 4, this is intrinsic properties of the material), wherein the first resistivity is higher than the second resistivity (fig. 4, inherently show this feature since 422b, 2DEG is formed within lower channel 408b, the lower channel having a heterojunction channel with higher electron mobility and/or very low resistance. Furthermore, they are the same material, i.e, GaN as the cited prior art); forming a back barrier layer 409 over the second GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AIN) (fig. 4); forming a third GaN layer 408a (fig. 4) over the back barrier layer, wherein the third GaN layer is formed to have a third resistivity (i.e., fig. 4, this is intrinsic properties of the material); forming a front barrier layer 410 (fig. 4) over the third GaN layer, wherein a 2-Dimensional Electron Gas (2-DEG) is provided in the third GaN layer 408a at a first interface between the third GaN layer 408a and the front barrier layer 410 (fig. 4); and forming a source electrode 416, a drain electrode 420 and a gate electrode 418 (fig. 4) over the front barrier layer, see figs. 1-30 and pages 1-28 for more details.
Re claim 8. The method of claim 7, wherein the front barrier layer comprises Aluminum Gallium Nitride (AlxGa1-xN), and wherein 0≤x≤1 (fig. 4 and paragraph 43).
Re claim 9. The method of claim 7, wherein the back barrier layer 409 is located under the third GaN layer 408a separated from the first interface by a first thickness of a first portion of the third GaN layer 408a (fig. 4).
Re claim 11. The method of claim 7, wherein a second thickness of the back barrier layer is in a range of 0.5 and 10 nanometers (paragraph 47).
Re claim 12. The method of claim 7, wherein electrons in the 2-DEG in the third GaN layer 408a at the first interface is blocked by a second interface between a first portion of the third GaN layer 408a and the back barrier layer 409 (fig. 4).
Re claim 14. Chen et al. disclose a method for manufacturing a High Electron Mobility Transistor, comprising: forming a first Gallium Nitride (GaN) layer 406 over a buffer layer 404 that is formed over a substrate 402, the first GaN layer being formed to have a first resistivity (i.e., fig. 4, this is intrinsic properties of the material); forming a second GaN layer 408b over the first GaN layer, the second GaN layer being formed to have a second resistivity that is lower than the first resistivity (fig. 4, inherently show this feature since 422b, 2DEG is formed within lower channel 408b, the lower channel having a heterojunction channel with higher electron mobility and/or very low resistance. Furthermore, they are the same material, i.e, GaN as the cited prior art); depositing a back barrier layer 409 (fig. 4) on the second GaN layer; forming a third GaN layer 408a (fig. 4) over the back barrier layer, the third GaN layer being formed to have a third resistivity that is lower than the first resistivity (fig. 4, inherently show this feature since 422a is formed within upper channel 408a; the upper channel having a higher electron mobility and/or very low resistance. Furthermore, they are the same material, i.e, GaN as the cited prior art); depositing a front barrier layer 410 (fig. 4) on the third GaN layer; and forming a source electrode 416, a drain electrode 420 and a gate electrode 418 (fig. 4) on the front barrier layer, wherein a 2-Dimensional Electron Gas (2-DEG) is provided in the third GaN layer 408a at a first interface between the third GaN layer 408a and the front barrier layer 410 (fig. 4), see figs. 1-30 and pages 1-28 for more details.
Re claim 15. The method of claim 14, wherein the front barrier layer comprises Aluminum Gallium Nitride (AlxGa1-xN), and wherein 0≤x≤1 (fig. 4 and paragraph 43).
Re claim 17. The method of claim 14, wherein a third thickness of the back barrier layer is in a range of 0.5 and 10 nanometers (paragraph 47).
Re claim 18. The method of claim 14, wherein electrons in the 2-DEG in the third GaN layer 408a at the first interface is blocked by a second interface between the third GaN layer 408a and the back barrier layer 409 (fig. 4).
Re claim 19. The method of claim 14, further comprising (due to 112 issues), preparing a buffer layer 404 or a lower portion of 406 on the substrate 402 (fig. 4).
Re claim 20. The method of claim 19, (due to 112 issues) wherein the buffer layer comprises AlyGal-yN (i.e., GaN when y=0).
Re claim 21, wherein the third resistivity of the third GaN layer is lower than the first resistivity of the first GaN layer (fig. 4, inherently show this feature since 422a is formed within upper channel 408a, the upper channel has a higher electron mobility and/or very low resistance. Furthermore, they are the same material, i.e, GaN as the cited prior art).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-6, 10, 13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al., WO-2017/000906 A1.
Re claim 1, Chen et al. disclose a method for manufacturing a High Electron Mobility Transistor, comprising: forming a first portion of a Gallium Nitride (GaN) layer408b (fig. 4 and paragraph 43); depositing a back barrier layer 409 (fig. 4 and paragraph 43, i.e., AlN, intrinsic properties of the material) on the first portion of the GaN layer; forming a second portion of the GaN layer 408a (fig. 4) over the back barrier layer; depositing a front barrier layer 410 (fig. 4) on the second portion of the GaN layer; and forming a source electrode 416, a drain electrode 420 and a gate electrode 418 (fig. 4) on the front barrier layer, wherein the back barrier layer comprises Aluminum Nitride (AIN) (fig. 4 and paragraph 43) and where a 2- Dimensional Electron Gas (2-DEG) in the second portion of the GaN layer at a first interface between the second portion of the GaN layer and the front barrier layer (fig. 4), see figs. 1-30 and pages 1-28 for more details.
Chen et al. disclose above; however, Chen does not explicitly show the thickness of the second portion of the GaN layer is in a range of 25 and 350 nanometers and the thickness of the first portion of the GaN layer is in a range of 300 and 1500 nanometers.
The thickness instant claim’s range of claim 1 is considered to involve routine optimization while has been held to be within the level of ordinary skill in the art. As noted in In re Aller, the selection of reaction parameters such as thickness, temperature and concentration etc. would have been obvious:
“Normally, it is to be expected that a change in temperature, or in concentration, or in both, would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art...such ranges are termed Acritical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.”
In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Therefore, one of ordinary skill in the requisite art before the invention was made would have used any thickness range suitable to the method of Chen et al. in order to optimize the process of the device etc. Further in this regard, the specification contains no disclosure of either the critical nature of the claimed arrangement (i.e. - the thickness of the second portion of the GaN layer is in a range of 25 and 350 nanometers and the thickness of the first portion of the GaN layer is in a range of 300 and 1500 nanometers) or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen limitations or upon another variable recited in a claim, the Applicant must show that the chosen limitations are critical. In re Woodruff, 919 F.2d 1575, 1578 (Fed. Cir. 1990). Note: nowhere in the Figs. 5A-5C and/or paragraphs 42-45 of specification show that the particular ranges (i.e. - the thickness of the second portion of the GaN layer is in a range of 25 and 350 nanometers and the thickness of the first portion of the GaN layer is in a range of 300 and 1500 nanometers) claimed produce a new and unexpected results.
Re claim 2. The method of claim 1, wherein the front barrier layer comprises Aluminum Gallium Nitride (AlxGa1-xN), and wherein 0≤x≤1 (fig. 4 and paragraph 43).
Re claim 4. The method of claim 1, wherein a third thickness of the back barrier layer is in a range of 0.5 and 10 nanometers (paragraph 47).
Re claim 5. The method of claim 1, wherein electrons in the 2-DEG in the second portion of the GaN layer at the first interface 410/408a is blocked by a second interface 408b/409 between the first portion of the GaN layer and the back barrier layer (fig. 4).
Re claim 6, Chen et al. further shows prior to the forming a first portion of a GaN layer 408b, preparing a buffer layer 406 on a Silicon (Si) substrate 402, wherein the buffer layer comprises AlyGal-yN (i.e., y=0, GaN) and forming a conductive GaN layer (fig. 4, ie., a lower portion of the 408b) on the buffer layer. However, Chen et al. does not explicitly state that
the Si substrate has a surface orientation of<111>.
Using Si substrate has a surface orientation of<111> has been well-known in the semiconductor art for forming a semiconductor device. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co., Inc. v. Interchemical Corp. , 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig - saw puzzle." 65 USPQ at 301.).
Therefore, the subject matter as a whole would have been obvious to one having ordinary skill in the art before the invention was made to use any suitable surface orientation of Si substrate in the method of Chen et al. in order to form the HEMT device.
Chen et al. disclose above; however, Chen does not explicitly show the instant claim thickness (Re claims 10, 13 and 16).
The thickness range of claims 10, 13 and 16 are considered to involve routine optimization while has been held to be within the level of ordinary skill in the art. As noted in In re Aller, the selection of reaction parameters such as thickness, temperature and concentration etc. would have been obvious:
“Normally, it is to be expected that a change in temperature, or in concentration, or in both, would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art...such ranges are termed Acritical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.”
In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Therefore, one of ordinary skill in the requisite art before the invention was made would have used any thickness range suitable to the method of Chen et al. in order to optimize the process of the device etc. Further in this regard, the specification contains no disclosure of either the critical nature of the claimed arrangement (i.e. - the thickness of the GaN layers) or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen limitations or upon another variable recited in a claim, the Applicant must show that the chosen limitations are critical. In re Woodruff, 919 F.2d 1575, 1578 (Fed. Cir. 1990).
Response to Arguments
Applicant's arguments filed 11/18/2025 have been fully considered but they are not persuasive for reasons herein above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK CHEN whose telephone number is (571)272-1689. The examiner can normally be reached Monday to Friday, 8am to 4pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACK S CHEN/ Primary Examiner, Art Unit 2893
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