DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 11/17/2023 and 05/29/2025 were filed before the first action on the merits. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 5-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al. (2015/0263172).
Re claim 1, Cho teaches a semiconductor device structure (Figs. 1-10), comprising: a first fin structure (F1) disposed at a first device region [38-39] and extending from a substrate (101) along a first direction (Y1), wherein the first fin structure (F1) comprises a first recess (141) formed in a top of the first fin structure (F1), the first recess (141) having a bottom and a sidewall extending upwardly from the bottom (Fig. 2), wherein the sidewall has a tapering profile [28]; a first source/drain feature (131) in contact with the first fin structure (F1); and a first gate structure (151) disposed in the first recess (141), the first gate structure (151) extending along a second direction (X1) perpendicular to the first direction (Y1), wherein the first gate structure (151) has a first gate dielectric layer (153), and the first gate dielectric layer (153) has a sidewall surface and a bottom surface in contact with the sidewall and the bottom of the first recess (141), respectively.
Re claim 2, Cho teaches the semiconductor device structure of claim 1, wherein the first gate structure (151) further comprises a first gate spacer (129) having a bottom surface in contact with a top surface of the sidewall of the first recess (Fig. 2).
Re claim 3, Cho teaches the semiconductor device structure of claim 2, wherein the bottom surface has a slope (Fig. 5).
Re claim 5, Cho teaches the semiconductor device structure of claim 1, wherein the bottom surface of the first gate spacer (129) has a lowest point at an elevation higher (Fig. 2) than the bottom of the first recess (141).
Re claim 6, Cho teaches the semiconductor device structure of claim 1, wherein the bottom of the first recess (141) is at an elevation lower than a top surface (Figs. 5-6) of the first source/drain feature (131).
Re claim 7, Cho teaches the semiconductor device structure of claim 1, further comprising: a second fin structure (F2) disposed at a second device region [38-39] and extending from the substrate (101) along the first direction (Y1), wherein the second fin (F2) comprises a second recess (141) formed in a top of the second fin structure (F2), the second recess (141) having a bottom and a sidewall extending upwardly from the bottom (Fig. 2), wherein the sidewall of the second recess has a tapering profile [28]; and a second gate structure (151) disposed in the second recess (141), the second gate structure (151) extending along the second direction (X1), wherein the second gate structure (151) has a second gate dielectric layer (153), and the second dielectric layer (153) has a sidewall surface and a bottom surface in contact with the sidewall and the bottom of the second recess (141), respectively.
Re claim 8, Cho teaches the semiconductor device structure of claim 7, wherein the second gate structure (151) further comprises a second gate spacer (129) having a sloped bottom surface in contact with a top surface of the sidewall of the second recess (141).
Re claim 9, Cho teaches the semiconductor device structure of claim 7, wherein the first fin structure (F1) is formed of silicon germanium [38-39] and the second fin structure (F2) is formed of silicon [38-39].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (2015/0263172) in view of the following reasons.
Re claim 10, Cho teaches the semiconductor device structure of claim 8, wherein the sidewall of the first recess has a first height and the sidewall of the second recess has a second height (Figs. 2-3).
Cho does not explicitly teach the second height greater than the first height.
However, Applicant has not shown wherein the second height greater than the first height has a specific, disclosed criticality that is unexpected and would not have been determined through routine experimentation of one having ordinary skill in the art. Therefore, it would have been obvious to adjust the sidewall heights so as to customize, optimize, or otherwise meet customer space and design requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (2015/0263172) in view of the following reasons.
Re claim 11, Cho teaches a semiconductor device structure (Figs. 1-10), comprising: a first source/drain feature (131) disposed in a first device region [39]; a first conductive feature (171) disposed over the first source/drain feature (131) a first fin structure (F1) disposed in the first device region [39] and in contact with the first source/drain feature (131); a first gate structure (151) disposed over the first fin structure (F1) and having a bottom extended a first distance into the first fin structure (Fig. 3); a second fin structure (F2) disposed in a second device region [38]; and a second gate structure (151) disposed over the second fin structure (F2) and having a bottom extended a second distance into the second fin structure (F3),
Cho does not explicitly teach wherein the first distance is different than the second distance.
However, Applicant has not shown wherein the first distance is different than the second distance has a specific, disclosed criticality that is unexpected and would not have been determined through routine experimentation of one having ordinary skill in the art. Therefore, it would have been obvious to adjust the first and second distances so as to customize, optimize, or otherwise meet customer space and design requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Prior art of record
Re claim 18, Cho et al. (2015/0263172) teaches a method for forming a semiconductor device structure (Figs. 1-31), comprising: forming first fin structure (F1) in a first device region [38-39] and second fin structure (F2) in a second device region [38-39]; forming a sacrificial gate structure (120) across the first (F1) and second (F2) fin structures; forming a gate spacer (129) on opposite sidewalls of the sacrificial gate structure (120); and recessing the first and second fin structures such that a top surface of each of the first and second fin structures not covered by the sacrificial gate structure (Figs. 20-22).
Cho does not explicitly teach wherein the gate spacer has a slope gradually decreasing in a direction away from the sacrificial gate structure.
Allowable Subject Matter
Claims 4 and 12-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re claim 4, Cho teaches the semiconductor device structure of claim 3, yet remains explicitly silent to wherein the slope is gradually decreased in height from the first gate structure towards the first source/drain feature.
Re claim 12, Cho teaches the semiconductor device structure of claim 11, yet remains explicitly silent to wherein the first gate structure further comprises a first gate spacer having a sloped bottom.
Claims 13 and 17 are objected to for at least depending from objected claim 12.
Re claim 14, Cho teaches the semiconductor device structure of claim 11, further comprising: a contact etch stop layer (CESL) (135) disposed over the first source/drain feature (131), yet remains explicitly silent to a contact sidewall dielectric layer disposed between the CESL and the first conductive feature above the first source/drain feature.
Claims 15 and 16 are objected to for at least depending from objected claim 14.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not anticipate or make obvious the method of claim 18, including each of the limitations and specifically wherein the gate spacer has a slope gradually decreasing in a direction away from the sacrificial gate structure, for the same reasons as mentioned for claim 18 in the prior art of record above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached M-F 9-5.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897